公开(公告)号：US20210110867A1

公开(公告)日：2021-04-15

申请号：US16709665

申请日：2019-12-10

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  El Mehdi Boujamaa

IPC: G11C11/419 ,  G11C11/16

Abstract: Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.

公开(公告)号：US20210110853A1

公开(公告)日：2021-04-15

申请号：US16600483

申请日：2019-10-12

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Nicolaas Klarinus Johannes van Windelhoff ,  Bo Zheng ,  El Mehdi Boujamaa ,  Fakhruddin Ali Bohra

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/418 ,  G11C11/16

Abstract: Various implementations described herein refer to a method for providing single port memory with a bitcell array arranged in columns and rows. The method may include coupling a wordline to the single port memory including coupling the wordline to the columns of the bitcell array. The method may include performing multiple memory access operations concurrently in the single port memory including performing a read operation in one column of the bitcell array using the wordline while performing a write operation in another column of the bitcell array using the wordline, or performing a write operation in one column of the bitcell array using the wordline while performing a read operation in another column of the bitcell array using the same wordline.

公开(公告)号：US10943670B1

公开(公告)日：2021-03-09

申请号：US16555964

申请日：2019-08-29

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Gaurav Rattan Singla

IPC: G11C7/14 ,  G11C5/06 ,  G11C8/14 ,  G11C29/00 ,  G11C11/4091 ,  G11C8/18 ,  G11C11/16

Abstract: Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.

公开(公告)号：US20190237135A1

公开(公告)日：2019-08-01

申请号：US15886630

申请日：2018-02-01

Applicant: Arm Limited

Inventor： Arjunesh Namboothiri Madhavan ,  Akash Bangalore Srinivasa ,  Sujit Kumar Rout ,  Vikash ,  Gaurav Rattan Singla ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Lalit Gupta

IPC: G11C11/419 ,  H01L29/94 ,  H01L27/11 ,  G11C7/12 ,  G11C7/18 ,  G11C8/16 ,  G11C7/10

CPC classification number: G11C11/419 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/16 ,  H01L27/1116 ,  H01L29/94

Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

公开(公告)号：US20190198064A1

公开(公告)日：2019-06-27

申请号：US15851341

申请日：2017-12-21

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C7/08 ,  G11C7/22 ,  G11C7/12

Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

公开(公告)号：US20190122724A1

公开(公告)日：2019-04-25

申请号：US15789715

申请日：2017-10-20

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra

IPC: G11C11/418 ,  G11C11/412 ,  H01L27/11 ,  H01L23/528

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.

公开(公告)号：US20180331681A1

公开(公告)日：2018-11-15

申请号：US16042949

申请日：2018-07-23

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03K17/22 ,  G11C5/14

CPC classification number: H03K17/223 ,  G11C5/148

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

公开(公告)号：US10033376B2

公开(公告)日：2018-07-24

申请号：US15143197

申请日：2016-04-29

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03L7/00 ,  H03K17/22 ,  G11C5/14

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.