公开(公告)号：US20230198772A1

公开(公告)日：2023-06-22

申请号：US17555020

申请日：2021-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Andrew G. Kegel

IPC: H04L9/32 ,  G06N3/08

CPC classification number: H04L9/3239 ,  G06N3/08

Abstract: An approach is provided for implementing a useful proof-of-work consensus algorithm. A proposed block is received. A combined hash value is generated based on the proposed block and a nonce value. The combined hash value is divided into a plurality of hash value pieces that each correspond to a work packet of a plurality of work packets. One or more requests are transmitted for the plurality of work packets that correspond to the plurality of hash value pieces. In response to receiving the plurality of work packets, a plurality of results is generated by performing, for each work packet of the plurality of work packets, one or more operations to complete work specified by the respective work packet. In response to determining that at least one result of the plurality of results satisfies one or more criteria, the proposed block is added to a blockchain maintained by the blockchain network.

公开(公告)号：US11341059B2

公开(公告)日：2022-05-24

申请号：US16894473

申请日：2020-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Andrew G. Kegel

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/1027 ,  G06F3/06

Abstract: The described embodiments include an input-output memory management unit (IOMMU) with two or more memory elements and a controller. The controller is configured to select, based on one or more factors, one or more selected memory elements from among the two or more memory elements for performing virtual address to physical address translations in the IOMMU. The controller then performs the virtual address to physical address translations using the one or more selected memory elements.

公开(公告)号：US10162765B2

公开(公告)日：2018-12-25

申请号：US15491616

申请日：2017-04-19

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Andrew G. Kegel ,  Anthony Asaro

IPC: G06F12/02 ,  G06F13/28 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081

Abstract: A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

公开(公告)号：US10078588B2

公开(公告)日：2018-09-18

申请号：US15081379

申请日：2016-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Mark H. Oskin ,  Gabriel H. Loh ,  Andrew G. Kegel ,  David S. Christie ,  Kevin J. McGrath

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1027

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1027 ,  G06F2212/1024 ,  G06F2212/657 ,  G06F2212/683 ,  G06F2212/684 ,  Y02D10/13

Abstract: The described embodiments include a computing device with two or more translation lookaside buffers (TLB) that performs operations for handling entries in the TLBs. During operation, the computing device maintains lease values for entries in the TLBs, the lease values representing times until leases for the entries expire, wherein a given entry in the TLB is invalid when the associated lease has expired. The computing device uses the lease value to control operations that are allowed to be performed using information from the entries in the TLBs. In addition, the computing device maintains, in a page table, longest lease values for page table entries indicating when corresponding longest leases for entries in TLBs expire. The longest lease values are used to determine when and if a TLB shootdown is to be performed.

公开(公告)号：US09798479B2

公开(公告)日：2017-10-24

申请号：US14931126

申请日：2015-11-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0683 ,  G06F12/023 ,  G06F12/1081 ,  G06F2212/1044

Abstract: The described embodiments include a computing device that performs operations for at least one of resizing or relocating a table in a memory in the computing device. In the described embodiments, the computing device includes at least one register storing a table base address indicating an original location of an original table in the memory and a table size indicating an original size of the original table in the memory. When relocating the original table, the computing device copies, using the table base address, some or all of the entries from the original table to a new table in the memory and then updates the table base address to indicate a location of the new table in the memory. When resizing the original table, the computing device updates the table size to indicate a new size.

公开(公告)号：US20170212851A1

公开(公告)日：2017-07-27

申请号：US15005378

申请日：2016-01-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Andrew G. Kegel

IPC: G06F13/24

Abstract: The described embodiments include a computing device with multiple interrupt processors for processing interrupts. In the described embodiments, each of the multiple processors is classified as one or more processor types based on factors such as features and functionality of the processor, an operating environment of the processor, the characteristics of some or all of the available interrupts, etc. During operation, an interrupt controller in the computing device receives an indication of an interrupt. The interrupt controller then determines a processor type for processing the interrupt. Next, the interrupt controller causes the interrupt to be processed by one of the plurality of processors that is the determined processor type.

公开(公告)号：US20170123693A1

公开(公告)日：2017-05-04

申请号：US14931126

申请日：2015-11-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0683 ,  G06F12/023 ,  G06F12/1081 ,  G06F2212/1044

Abstract: The described embodiments include a computing device that performs operations for at least one of resizing or relocating a table in a memory in the computing device. In the described embodiments, the computing device includes at least one register storing a table base address indicating an original location of an original table in the memory and a table size indicating an original size of the original table in the memory. When relocating the original table, the computing device copies, using the table base address, some or all of the entries from the original table to a new table in the memory and then updates the table base address to indicate a location of the new table in the memory. When resizing the original table, the computing device updates the table size to indicate a new size.

公开(公告)号：US09489173B2

公开(公告)日：2016-11-08

申请号：US14296373

申请日：2014-06-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel

IPC: G06F5/08 ,  G06F5/06 ,  G06F5/10

CPC classification number: G06F5/085 ,  G06F5/065 ,  G06F5/10 ,  G06F2205/063 ,  G06F2205/064

Abstract: A computing device with a queue stored in a memory of the computing device is described. The queue may be relocated and/or resized in the memory using a queue address, a queue size, a head pointer, and/or a tail pointer associated with the queue. During operation, a processor, at the request of a software entity, updates one or more values associated with the queue to relocate and/or resize the queue. In response, a write mechanism performs one or more operations to enable the use of the relocated and/or resized queue. In addition, when the queue is relocated, the processor, at the request of the software entity, performs one or more operations to process remaining valid entries in an original location of the queue.

Abstract translation: 描述了具有存储在计算设备的存储器中的队列的计算设备。 队列可以使用与队列相关联的队列地址，队列大小，头指针和/或尾部指针在存储器中重新定位和/或调整大小。 在操作期间，处理器在软件实体的请求下更新与队列相关联的一个或多个值以重新定位和/或调整队列大小。 作为响应，写入机制执行一个或多个操作以使得能够使用重定位和/或调整大小的队列。 此外，当重新定位队列时，处理器在软件实体的请求下执行一个或多个操作以处理队列的原始位置中的剩余有效条目。

公开(公告)号：US20160246540A1

公开(公告)日：2016-08-25

申请号：US14629014

申请日：2015-02-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Andrew G. Kegel

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0647 ,  G06F3/0607 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/0215 ,  G06F2212/654

Abstract: In one form, scheduling data migration comprises determining whether the data is likely to be used by an input/output (I/O) device, the data being at a location remote to the I/O device; and scheduling the data for migration from the remote location to a location local to the I/O device in response to determining that the data is likely to be used by the I/O device.

Abstract translation: 在一种形式中，调度数据迁移包括确定数据是否可能被输入/输出（I / O）设备使用，该数据位于远离I / O设备的位置; 并且响应于确定数据可能被I / O设备使用而调度用于从远程位置迁移到I / O设备本地的位置的数据。

公开(公告)号：US20160224397A1

公开(公告)日：2016-08-04

申请号：US14610662

申请日：2015-01-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Manish Arora ,  Can Hankendi ,  Syed Ali R. Jafri ,  Andrew G. Kegel

IPC: G06F9/52 ,  G11C7/10 ,  G06F12/02 ,  G06F9/50 ,  G06F9/46

CPC classification number: G06F9/485 ,  G06F12/0246 ,  G06F2212/7201 ,  H04W4/02 ,  H04W4/029 ,  H04W4/50

Abstract: In one form, a data processing system includes volatile and non-volatile memory, a central processing unit, and at least one peripheral device. The central processing unit executes a selected one of a plurality of software applications as directed by an operating system by transferring the selected software application from the non-volatile memory to the volatile memory and executing instructions associated with the selected software application from the volatile memory. The at least one peripheral device includes a real-time clock for defining execution contexts for the plurality of software applications. The data processing system further includes a usage pattern analyzer adapted to store history information associated with an execution context for each of the plurality of software applications, and to use the history information to direct the operating system to take at least one action based on the history information.

Abstract translation: 在一种形式中，数据处理系统包括易失性和非易失性存储器，中央处理单元和至少一个外围设备。 中央处理单元通过将所选择的软件应用程序从非易失性存储器传送到易失性存储器并且从易失性存储器执行与所选择的软件应用程序相关联的指令，由操作系统指导执行多个软件应用程序中的选定的一个。 所述至少一个外围设备包括用于定义多个软件应用的执行上下文的实时时钟。 所述数据处理系统还包括使用模式分析器，其适于存储与所述多个软件应用中的每一个的执行上下文相关联的历史信息，并且使用所述历史信息来指示所述操作系统基于所述历史记录采取至少一个动作 信息。