公开(公告)号：US20080168217A1

公开(公告)日：2008-07-10

申请号：US11650120

申请日：2007-01-05

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G06F12/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615

摘要： A memory device includes a memory array containing a plurality of memory addresses. An input terminal receives a requested one of the memory addresses and a memory controller is configured to refresh a first refresh address in response to a comparison of the received memory address and the first refresh address. In certain embodiments, the first refresh address is refreshed if it does not conflict with the received memory. If the first refresh address and the received memory address conflict, a second refresh address is refreshed. The received memory address is accessed simultaneously with the refresh in exemplary embodiments.

摘要翻译： 存储器件包括包含多个存储器地址的存储器阵列。 输入终端接收所请求的一个存储器地址，并且存储器控制器被配置为响应于所接收的存储器地址与第一刷新地址的比较来刷新第一刷新地址。 在某些实施例中，如果第一刷新地址与所接收的存储器不冲突，则刷新第一刷新地址。 如果第一个刷新地址和接收到的存储器地址冲突，则刷新第二个刷新地址。 在示例性实施例中，与刷新同时访问所接收的存储器地址。

公开(公告)号：US07254089B2

公开(公告)日：2007-08-07

申请号：US11025561

申请日：2004-12-29

申请人： Thomas Vogelsang ,  Harald Lorenz ,  Wolfgang Hokenmaier

发明人： Thomas Vogelsang ,  Harald Lorenz ,  Wolfgang Hokenmaier

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C11/405 ,  G11C11/4087 ,  G11C2211/4013

摘要： A memory circuit comprises a memory including a memory array, a twin cell mode predecoder, and a row address predecoder. The memory array comprises word lines. The twin cell mode predecoder is configured for selecting one of four word line activation configurations for the memory array. The four word line activation configurations include three twin cell word line activation configurations and a single cell word line activation configuration. The row address predecoder is configured for selecting one of four word lines if the single cell word line activation configuration is selected.

摘要翻译： 存储器电路包括存储器，其包括存储器阵列，双单元模式预解码器和行地址预解码器。 存储器阵列包括字线。 双胞胎模式预解码器被配置用于选择存储器阵列的四个字线激活配置之一。 四个字线激活配置包括三个双胞胎字线激活配置和单个单元格字线激活配置。 行地址预解码器被配置为如果选择了单个单元字线激活配置，则选择四个字线之一。

公开(公告)号：US07060566B2

公开(公告)日：2006-06-13

申请号：US10873010

申请日：2004-06-22

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： H01L21/336

CPC分类号： H03K19/0013 ,  H01L27/0925 ,  H01L27/0928 ,  Y10S257/901

摘要： An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of the MOSFETs. After die processing, a post-processing test is performed to measure an operating characteristic of the die such as leakage current or switching speed, and an external voltage source is applied and adjusted to control the operating characteristic. The on-die fuses are then cleared to adjust the on-die voltage source to match the externally applied voltage. The operating characteristic may be determined by including a test circuit on the die to exhibit the operating characteristic such as a ring oscillator frequency. This approach to controlling manufacturing-induced device performance variations is well suited to efficient manufacture of small feature-size circuits such as DRAMs.

摘要翻译： 在具有欧姆接触的衬底上形成包括具有相似类型和几何形状的多个MOSFET的集成电路器件，并且使用可清除熔丝的管芯上的可调电压源耦合在欧姆接触和MOSFET的源极之间。 在模具处理之后，进行后处理试验以测量管芯的工作特性，例如漏电流或开关速度，施加外部电压源并进行调整以控制工作特性。 然后清除管芯内保险丝以调整片上电压源以匹配外部施加的电压。 操作特性可以通过在芯片上包括测试电路来表现出诸如环形振荡器频率的工作特性来确定。 用于控制制造引起的器件性能变化的这种方法非常适合于诸如DRAM的小型特征尺寸电路的有效制造。

公开(公告)号：US20050110523A1

公开(公告)日：2005-05-26

申请号：US10720437

申请日：2003-11-24

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： H03K5/12 ,  H03K5/1252 ,  H03K19/096

CPC分类号： H03K5/12 ,  H03K5/1252

摘要： A clock filter for use in filtering an external clock signal to create an internal clock signal for use by an electronic device is provided. The clock filter receives the external clock signal and sets the internal clock signal high when the external clock signal is above a first threshold and sets the internal clock signal low when the external clock signal is below a second threshold. The clock filter holds the internal clock signal constant for a period of time after the clock transitions.

摘要翻译： 提供了一种用于对外部时钟信号进行滤波以产生电子设备使用的内部时钟信号的时钟滤波器。 当外部时钟信号高于第一阈值时，时钟滤波器接收外部时钟信号并将内部时钟信号设置为高电平，并且当外部时钟信号低于第二阈值时将内部时钟信号设置为低电平。 时钟滤波器在时钟转换后的一段时间内保持内部时钟信号恒定。

公开(公告)号：US06369606B1

公开(公告)日：2002-04-09

申请号：US09670945

申请日：2000-09-27

申请人： Russell J. Houghton ,  William R. Tonti ,  Thomas Vogelsang ,  Adam B. Wilson

发明人： Russell J. Houghton ,  William R. Tonti ,  Thomas Vogelsang ,  Adam B. Wilson

IPC分类号： H03K1923

CPC分类号： H03K19/0948 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H03K19/0963

摘要： A logic circuit implementing a logic function and method of manufacture thereof. The logic circuit includes a series connection of two or more CMOS devices, at least one CMOS device having a threshold voltage at an input lower than a threshold voltage at an input of another of the CMOS devices. The CMOS logic circuit exhibits enhanced switching speed for logic operations and reduced leakage current when operating in an off-state. A logic family is built around the series connection of two or more devices having mixed voltage threshold inputs for enhanced switching speed and reduced off-current leakage.

摘要翻译： 实现逻辑功能的逻辑电路及其制造方法。 逻辑电路包括两个或更多个CMOS器件的串联连接，至少一个CMOS器件在另一个CMOS器件的输入处具有低于阈值电压的输入处的阈值电压。 CMOS逻辑电路表现出增强的逻辑运算开关速度，并且在关断状态下运行时具有降低的漏电流。 逻辑系列是围绕具有混合电压阈值输入的两个或多个器件的串联连接构成的，以提高开关速度和减少的漏电流。

公开(公告)号：US6160747A

公开(公告)日：2000-12-12

申请号：US322718

申请日：1999-05-28

申请人： Martin Brox ,  Helmut Schneider ,  Thomas Vogelsang ,  Michael Killian

发明人： Martin Brox ,  Helmut Schneider ,  Thomas Vogelsang ,  Michael Killian

IPC分类号： G11C8/08 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C8/08

摘要： A configuration for crosstalk attenuation in substantially mutually parallel word lines of DRAM circuits, includes a decoder provided at a first end of a word line, and a holding transistor. A pull-down device is provided as a "noise killer" at a second end of the word line, which opposite the first end. The pull-down device pulls down the potential of the word line in a standby and hold mode in the event of an active adjacent word line.

摘要翻译： 在DRAM电路的基本相互平行的字线中的串扰衰减的配置包括设置在字线的第一端的解码器和保持晶体管。 在与第一端相对的字线的第二端处提供下拉装置作为“噪声抑制器”。 在有效的相邻字线的情况下，下拉装置在待机和保持模式下拉下字线的电位。

公开(公告)号：US5443992A

公开(公告)日：1995-08-22

申请号：US332733

申请日：1994-11-01

申请人： Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

发明人： Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L21/265 ,  H01L21/20 ,  H01L21/302 ,  H01L21/76

CPC分类号： H01L29/66666 ,  H01L27/092 ,  H01L29/7827 ,  H01L29/42368

摘要： An insulating layer is grown on a principal face of a substrate that comprises a source terminal region. A first opening wherein the surface of the source terminal region is partially uncovered is provided in the insulating layer. A vertical layer sequence that comprises at least a channel region and a drain region for the MOS transistor is produced in the first opening by epitaxial growth of semiconductor material within situ doping. A second opening that is at least of a depth corresponding to the sum of the thicknesses of drain region and channel region is produced in the layer structure, a gate dielectric is applied on the surface thereof and a gate-electrode is applied on said gate dielectric.

摘要翻译： 在包括源极端子区域的基板的主面上生长绝缘层。 在绝缘层中设置有源极端子区域的表面部分未覆盖的第一开口。 在第一开口中通过外延生长半导体材料在原位掺杂中产生至少包括MOS晶体管的沟道区和漏极区的垂直层序列。 在层结构中产生至少具有与漏极区域和沟道区域的厚度之和相对应的深度的第二开口，在其表面上施加栅极电介质，并且在所述栅极电介质上施加栅极电极 。

公开(公告)号：US09214219B2

公开(公告)日：2015-12-15

申请号：US14238921

申请日：2012-08-27

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G11C7/00 ,  G11C11/4091 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097 ,  G11C5/02 ,  G11C7/08 ,  G11C8/12

CPC分类号： G11C11/4091 ,  G11C5/025 ,  G11C7/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4097

摘要： Described are dynamic, random-access memories (DRAM) architectures and methods for subdividing memory activation into fractions of a page. Circuitry in support of sub-page activation is placed in the intersections of local wordline drivers and sense-amplifier stripes to allow independent control of adjacent arrays of memory cells without significant area overhead.

摘要翻译： 描述了动态，随机存取存储器（DRAM）架构和用于将存储器激活细分为页面的分数的方法。 支持子页面激活的电路放置在本地字线驱动器和读出放大器条纹的交叉点中，以允许对存储器单元的相邻阵列的独立控制，而没有显着的面积开销。

公开(公告)号：US09001606B2

公开(公告)日：2015-04-07

申请号：US13703339

申请日：2011-08-22

申请人： Thomas Vogelsang ,  Brent Haukness

发明人： Thomas Vogelsang ,  Brent Haukness

IPC分类号： G11C7/02 ,  G11C5/14 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C5/147 ,  G11C7/00 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

摘要： A memory system includes wordlines and pairs of complementary bitlines that provide access to memory storage elements. Capacitive and resistive loads associated with wordlines and bitlines are driven relatively slowly between voltage levels to reduce peak current, and thus power dissipation. Power dissipation is further reduced by charging complementary bitlines at substantially different rates.

摘要翻译： 存储器系统包括提供对存储器存储元件的访问的字线和互补位线对。 与字线和位线相关的电容和电阻负载在电压电平之间相对较慢地驱动，以降低峰值电流，从而降低功耗。 通过以基本不同的速率充电补充位线来进一步降低功耗。

公开(公告)号：US08930779B2

公开(公告)日：2015-01-06

申请号：US13505449

申请日：2010-11-10

申请人： Frederick A. Ware ,  Ely Tsern ,  Thomas Vogelsang

发明人： Frederick A. Ware ,  Ely Tsern ,  Thomas Vogelsang

IPC分类号： G11C29/00 ,  G11C29/50 ,  G06F11/10 ,  G11C11/401

CPC分类号： G11C29/50016 ,  G06F11/1064 ,  G11C11/401 ,  G11C29/808

摘要： The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells.

摘要翻译： 所公开的实施例提供了一种动态存储器设备，其包括一组动态存储器单元和一组替换动态存储器单元。 替换动态存储器单元的集合包括包含用于动态存储器单元组中的预定故障单元的替换数据位的数据单元，以及包含标识故障单元的地址位的地址单元，其中每个数据单元与一组地址相关联 识别动态存储器单元组中相关联的故障单元的单元。 动态存储设备还包括重新映射电路，其将该组动态存储器单元中的故障单元重新映射到该替换单元组中的相关联的替换单元。