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327 条记录 (耗时 0.047 秒)

    Fracturable lookup table and logic element
    42.
    发明授权
    Fracturable lookup table and logic element 有权
    可破坏的查找表和逻辑元素

    公开(公告)号：US07323902B2

    公开(公告)日：2008-01-29

    申请号：US11189549

    申请日：2005-07-25

    申请人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy L. Lee

    发明人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy L. Lee

    IPC分类号： G06F7/38 ,  H03K19/177

    CPC分类号： H03K19/17728 ,  H03K19/1737

    摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

    摘要翻译： 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输入端的输出端和第一级多路复用器，其输入端连接到第二级 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。

    SOFT ERROR LOCATION AND SENSITIVITY DETECTION FOR PROGRAMMABLE DEVICES
    43.
    发明申请
    SOFT ERROR LOCATION AND SENSITIVITY DETECTION FOR PROGRAMMABLE DEVICES 有权
    可编程器件的软错误位置和灵敏度检测

    公开(公告)号：US20070283193A1

    公开(公告)日：2007-12-06

    申请号：US11737089

    申请日：2007-04-18

    申请人： David Lewis ,  Ninh D. Ngo ,  Andy L. Lee ,  Joseph Huang

    发明人： David Lewis ,  Ninh D. Ngo ,  Andy L. Lee ,  Joseph Huang

    IPC分类号： G06F11/10

    CPC分类号： G11C29/52 ,  G06F11/1064 ,  H03K19/17764

    摘要： Circuits, methods, and apparatus that detect whether a soft error that occurs in stored configuration data is a false positive that can be ignored such that reloading configuration data or other remedial measures are not unnecessarily performed. One example provides an integrated circuit including an error detection circuit and a sensitivity processor. The error detection circuit detects the presence of errors. The sensitivity processor determines whether a detected error can be ignored, or whether remedial action, such as providing an error flag, reconfiguring the device, or correcting the error, should be commenced. The sensitivity processor may make this determination based on whether the error occurred in a memory cell that configures unused circuitry. The sensitivity processor may make use of an error log to track known errors that may be ignored, so that this determination does not need to be done each time the configuration data is checked.

    摘要翻译： 检测在存储的配置数据中发生的软错误是否可以被忽略的假阳性的电路，方法和装置，使得不必要地重新加载配置数据或其他补救措施。 一个例子提供了包括错误检测电路和灵敏度处理器的集成电路。 误差检测电路检测出错误。 灵敏度处理器确定是否可以忽略检测到的错误，或者是否开始补救措施，例如提供错误标志，重新配置设备或纠正错误。 灵敏度处理器可以基于是否在配置未使用的电路的存储器单元中发生错误来进行该确定。 灵敏度处理器可以使用错误日志来跟踪可能被忽略的已知错误，使得每次检查配置数据时不需要完成该确定。

    Multiple size memories in a programmable logic device
    44.
    发明授权
    Multiple size memories in a programmable logic device 有权
    可编程逻辑器件中的多个大小的存储器

    公开(公告)号：US07236008B1

    公开(公告)日：2007-06-26

    申请号：US11611122

    申请日：2006-12-14

    申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Lewis

    发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Lewis

    IPC分类号： G06F7/38 ,  H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/17728

    摘要： Circuits, methods, and apparatus that provide integrated circuits having memories with multiple sizes. The memories may be dedicated embedded memories, or they may be distributed memories formed using memories or lookup tables in logic elements or other appropriate circuits. Configuration bits not needed by logic elements used for distributed memories can be used for data storage as well. These various memories may be combined or otherwise linked or chained together in different combinations to form larger memories of varying sizes.

    摘要翻译： 提供具有多种尺寸的存储器的集成电路的电路，方法和装置。 存储器可以是专用的嵌入式存储器，或者它们可以是使用逻辑元件或其他适当电路中的存储器或查找表形成的分布式存储器。 用于分布式存储器的逻辑元件不需要的配置位也可以用于数据存储。 这些各种存储器可以以不同的组合组合或以其他方式链接或链接在一起以形成不同大小的较大存储器。

    Structures for LUT-based arithmetic in PLDs
    45.
    发明授权
    Structures for LUT-based arithmetic in PLDs 有权
    在PLD中基于LUT的算术的结构

    公开(公告)号：US08788550B1

    公开(公告)日：2014-07-22

    申请号：US12484010

    申请日：2009-06-12

    申请人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

    发明人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

    IPC分类号： G06F7/38

    CPC分类号： G06F7/575 ,  H03K19/177 ,  H03K19/17728

    摘要： A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

    摘要翻译： 可编程逻辑器件（PLD）包括通过PLD路由架构连接的多个逻辑阵列块（LAB）。 至少一个LAB包括可配置为在多个级中算术组合多个二进制输入信号的逻辑元件（LE）。 LE包括具有K个输入（“K-LUT”）的查找表（LUT）逻辑。 K-LUT被配置为在K-LUT逻辑单元的相应输入处输入二进制输入信号，并且在K-LUT逻辑单元的多个输出处提供指示至少两个 二进制输入信号的算术组合的多级。 输入线网络包括输入线路网络，输入线路可配置为从PLD路由架构接收代表二进制输入信号的输入信号，并将输入信号提供给K-LUT。 输出线网络包括输出线网络，输出线路被配置为从K-LUT接收表示二进制结果信号的输出信号，并向PLD路由架构提供输出信号。 所描述的LUT可以有效地执行算术，以及非算术函数。

    Soft error location and sensitivity detection for programmable devices
    47.
    发明授权
    Soft error location and sensitivity detection for programmable devices 有权
    可编程器件的软错误位置和灵敏度检测

    公开(公告)号：US07702978B2

    公开(公告)日：2010-04-20

    申请号：US11737089

    申请日：2007-04-18

    申请人： David Lewis ,  Ninh D. Ngo ,  Andy L. Lee ,  Joseph Huang

    发明人： David Lewis ,  Ninh D. Ngo ,  Andy L. Lee ,  Joseph Huang

    IPC分类号： G06F11/00 ,  G01R31/28

    CPC分类号： G11C29/52 ,  G06F11/1064 ,  H03K19/17764

    摘要： Circuits, methods, and apparatus that detect whether a soft error that occurs in stored configuration data is a false positive that can be ignored such that reloading configuration data or other remedial measures are not unnecessarily performed. One example provides an integrated circuit including an error detection circuit and a sensitivity processor. The error detection circuit detects the presence of errors. The sensitivity processor determines whether a detected error can be ignored, or whether remedial action, such as providing an error flag, reconfiguring the device, or correcting the error, should be commenced. The sensitivity processor may make this determination based on whether the error occurred in a memory cell that configures unused circuitry. The sensitivity processor may make use of an error log to track known errors that may be ignored, so that this determination does not need to be done each time the configuration data is checked.

    摘要翻译： 检测在存储的配置数据中发生的软错误是否可以被忽略的假阳性的电路，方法和装置，使得不必要地重新加载配置数据或其他补救措施。 一个例子提供了包括错误检测电路和灵敏度处理器的集成电路。 误差检测电路检测出错误。 灵敏度处理器确定是否可以忽略检测到的错误，或者是否开始补救措施，例如提供错误标志，重新配置设备或纠正错误。 灵敏度处理器可以基于是否在配置未使用的电路的存储器单元中发生错误来进行该确定。 灵敏度处理器可以使用错误日志来跟踪可能被忽略的已知错误，使得每次检查配置数据时不需要完成该确定。

    Apparatus for field-programmable gate array with configurable architecture and associated methods
    49.
    发明授权
    Apparatus for field-programmable gate array with configurable architecture and associated methods 有权
    具有可配置架构和相关方法的现场可编程门阵列的装置

    公开(公告)号：US09165931B1

    公开(公告)日：2015-10-20

    申请号：US14187185

    申请日：2014-02-21

    申请人： Herman Schmit ,  David Lewis ,  Michael D. Hutton ,  Dana How ,  Andy L. Lee

    发明人： Herman Schmit ,  David Lewis ,  Michael D. Hutton ,  Dana How ,  Andy L. Lee

    IPC分类号： H01L27/115 ,  G06F17/50 ,  H01L27/105

    CPC分类号： G06F17/5054 ,  G06F15/7867 ,  H01L27/115 ,  H03K19/17728

    摘要： An integrated circuit (IC) includes a substrate that is common to the IC and variants of the IC. The IC also includes a first set of interconnect layers fabricated above the substrate. The first set of interconnect layers is used to couple programmable interconnect of the IC to a first circuit in the substrate. The IC further includes a second set of interconnect layers fabricated above the substrate. The second set of interconnect layers is used to differentiate features of the IC from variants of the IC by selectively coupling the programmable interconnect to a second circuit in the substrate.

    摘要翻译： 集成电路（IC）包括IC的通用基板和IC的变体。 IC还包括在衬底上方制造的第一组互连层。 第一组互连层用于将IC的可编程互连件耦合到衬底中的第一电路。 IC还包括在衬底上方制造的第二组互连层。 第二组互连层用于通过选择性地将可编程互连连接到衬底中的第二电路来区分IC的特征与IC的变体。