公开(公告)号：US20090107840A1

公开(公告)日：2009-04-30

申请号：US12257683

申请日：2008-10-24

申请人： Jayson Tessier ,  Carl Duchesne ,  Claude Gauthier ,  Gilles Dufour

发明人： Jayson Tessier ,  Carl Duchesne ,  Claude Gauthier ,  Gilles Dufour

IPC分类号： G01N27/26

CPC分类号： C25C3/20 ,  C25C3/14 ,  G01N2021/8427

摘要： Systems and methods for determining compositions of cover materials for electrolysis cells are provided. In one embodiment a system includes an aluminum electrolysis cell adapted to contain an electrolytic bath, a hopper configured to provide a cover material to the aluminum electrolysis cell, where the cover material includes alumina and electrolytic bath particulate, an imaging device configured to capture images of the cover material, an image processor configured to analyze the images and output imaging data relating to the cover material, and a data analyzer configured to analyze the imaging data and output a determined cover material composition in the form of cover material information. The cover material information may be used to manage operation of the aluminum electrolysis cell, such as via adjusting the composition or feed rate of the cover material.

摘要翻译： 提供了用于确定电解槽的覆盖材料组成的系统和方法。 在一个实施例中，系统包括适于容纳电解浴的铝电解池，配置成向铝电解池提供覆盖材料的料斗，其中覆盖材料包括氧化铝和电解浴颗粒，成像装置被配置为捕获 覆盖材料，被配置为分析图像并输出与覆盖材料相关的成像数据的图像处理器，以及配置成分析成像数据并以覆盖材料信息的形式输出确定的覆盖材料组成的数据分析器。 覆盖材料信息可以用于管理铝电解池的操作，例如通过调节覆盖材料的组成或进料速率。

公开(公告)号：US07509515B2

公开(公告)日：2009-03-24

申请号：US11231193

申请日：2005-09-19

申请人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F1/00

CPC分类号： G06F1/04 ,  G06F1/10 ,  H04L7/0012 ,  H04L7/033

摘要： A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.

摘要翻译： 描述了通过双向数据链路将客户端相位信息发送到主机设备的系统和方法。 实施例包括相对于通过双向数据链路在主机设备和客户端设备之间传输的数据信号检测时钟信号的相位。 数据链路包括一个或多个数据线，每个数据线被配置为传送数据信号的相应位。 该相位被编码为客户端相位信息，并通过一个或多个数据线在主机和客户端设备之间传输。 客户端相位信息是在数据链路上的读取和写入操作之间的双向数据链路的电气周转时间周期期间发送的。

公开(公告)号：US20050168255A1

公开(公告)日：2005-08-04

申请号：US10771989

申请日：2004-02-04

申请人： Claude Gauthier ,  Pradeep Trivedi ,  Raymond Heald ,  Gin Yee

发明人： Claude Gauthier ,  Pradeep Trivedi ,  Raymond Heald ,  Gin Yee

IPC分类号： G01R31/317 ,  H03B1/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/18

CPC分类号： H03L7/18 ,  G01R31/31727 ,  G06F2217/76 ,  H03L7/0812 ,  H03L7/0893

摘要： A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

摘要翻译： 一种用于补偿集成电路性能的年龄相关退化的方法和装置。 在一个实施例中，锁相环（PLL）电荷泵设置有多个支脚，其可以选择性地启用或禁用以补偿老化的影响。 在替代实施例中，可以增加或减少电源电压控制代码以补偿老化效应。 在另一个实施例中，环形振荡器用于近似NBTI的影响。 在本实施例中，使用数字计数器将频域转换为时域，并且使用可编程电源控制字来改变电源的操作参数以补偿老化效应。

公开(公告)号：US5155648A

公开(公告)日：1992-10-13

申请号：US661147

申请日：1991-02-27

申请人： Claude Gauthier

发明人： Claude Gauthier

IPC分类号： H02H9/02 ,  H02H9/00 ,  H02H9/04 ,  H02J1/00 ,  H04B15/02

CPC分类号： H04B15/02 ,  H02H9/004 ,  Y10S323/908

摘要： A device for protecting a direct current electrical power supply from disturbances caused by connecting to it or disconnecting from it an electronic system comprises at least one variable impedance component. The impedance of this component is controlled so that it has a very high first value when said electronic system is disconnected, a very low second value when said system is connected, a value varying slowly from said first value to said second value on changing from the disconnected state to the connected state and a value varying quickly from said second value to said first value on changing from the connected state to the disconnected state. The output current from said variable impedance component constitutes the supply current of said electronic system.

摘要翻译： 一种用于保护直流电源免受连接或断开电子系统所引起的干扰的装置包括至少一个可变阻抗分量。 控制该组件的阻抗，使得当所述电子系统断开时，其具有非常高的第一值，当所述系统连接时具有非常低的第二值，在从所述第一值到 断开状态到连接状态，以及在从连接状态变为断开状态时，从所述第二值快速变化到所述第一值的值。 来自所述可变阻抗部件的输出电流构成所述电子系统的供电电流。

公开(公告)号：US4952795A

公开(公告)日：1990-08-28

申请号：US458268

申请日：1989-12-29

申请人： Claude Gauthier ,  Guy Balland

发明人： Claude Gauthier ,  Guy Balland

IPC分类号： H03G7/00 ,  H03G3/20 ,  H03G11/02 ,  H04B10/04 ,  H04B10/06 ,  H04B10/14 ,  H04B10/26 ,  H04B10/28

CPC分类号： H03G3/3084 ,  H03G11/02

摘要： A current limiter circuit receiving an input current having a non-zero DC component whose value lies in a wide range of current values, and delivering a limited output current whose value lies in a narrower range of current values. The limiter comprises a series connection of a first asymmetrical conductivity element followed by a second asymmetrical conductivity element which is followed in turn by a resistive element, the series connection extending between two poles of a voltage source so that a bias current flows through the asymmetrical conductivity elements and makes them conductive. The input current is applied to the common point between the two asymmetrical conductivity elements and the current-limited output is taken from the common point between the second asymmetrical conductivity element and the resistive element. The direction of the input current flow is such that it splits into two fractions, with one of the fractions being subtracted from the bias current in the second asymmetrical conductivity element, while the other fraction is added to the bias current in the first asymmetrical conducitivity element, thereby increasing the dynamic resistance of the second asymmetrical conductivity element and reducing the dynamic resistance of the asymmetrical conductivity element, thus limiting the output current.

摘要翻译： 接收具有非零DC分量的输入电流的电流限制器电路，其值位于宽的电流值范围内，并传递值在较窄的电流值范围内的有限的输出电流。 限制器包括第一不对称导电元件和第二不对称导电元件的串联连接，第二非对称导电元件随后由电阻元件依次连接，该串联连接在电压源的两极之间延伸，使得偏置电流流过不对称电导率 元件并使其导电。 输入电流被施加到两个不对称导电元件之间的公共点，并且限流输出取自第二不对称导电元件和电阻元件之间的公共点。 输入电流的方向是分为两部分，其中一个部分从第二不对称导电元件中的偏置电流中减去，而另一部分被加到第一不对称导通元件中的偏置电流 从而增加第二不对称导电元件的动态电阻并降低不对称导电元件的动态电阻，从而限制输出电流。

公开(公告)号：US08892963B2

公开(公告)日：2014-11-18

申请号：US11595619

申请日：2006-11-09

申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F11/00 ,  H04L1/00 ,  G06F11/10 ,  G06F11/08

CPC分类号： H04L1/0045 ,  G06F11/08 ,  G06F11/10 ,  H04L1/0061 ,  H04L2001/0094

摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件通过接口的READ和WRITE操作同时从一个接口的一行接收第二个组件的签名。 与从第二组件到第一组件的签名传输相关联的延迟是第二组件计算签名所花费的时间。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于特定的READ或WRITE命令。 基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

公开(公告)号：US08301930B2

公开(公告)日：2012-10-30

申请号：US12356804

申请日：2009-01-21

申请人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00

CPC分类号： H04L7/02 ,  H04L7/0025 ,  H04L7/0091

摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

摘要翻译： 描述了非对称IO方法和系统。 在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。 共享资源包括一个共享相位内插器。 在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

公开(公告)号：US07996731B2

公开(公告)日：2011-08-09

申请号：US11592074

申请日：2006-11-01

申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F11/00

CPC分类号： G06F11/10

摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于接口上的事务。 基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

公开(公告)号：US07934109B2

公开(公告)日：2011-04-26

申请号：US11732783

申请日：2007-04-03

申请人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

发明人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju E. Lee ,  Lin Chen

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

摘要： Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.

摘要翻译： 描述用于存储器接口的功耗降低过程的实施例。 电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

公开(公告)号：US20070104327A1

公开(公告)日：2007-05-10

申请号：US11595619

申请日：2006-11-09

申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

IPC分类号： H04N7/167

CPC分类号： H04L1/0045 ,  G06F11/08 ,  G06F11/10 ,  H04L1/0061 ,  H04L2001/0094

摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件通过接口的READ和WRITE操作同时从一个接口的一行接收第二个组件的签名。 与从第二组件到第一组件的签名传输相关联的延迟是第二组件计算签名所花费的时间。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于特定的READ或WRITE命令。 基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。