公开(公告)号：US20070067661A1

公开(公告)日：2007-03-22

申请号：US11231193

申请日：2005-09-19

申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

IPC分类号： G06F1/04

CPC分类号： G06F1/04 ,  G06F1/10 ,  H04L7/0012 ,  H04L7/033

摘要： A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.

摘要翻译： 描述了通过双向数据链路将客户端相位信息发送到主机设备的系统和方法。 实施例包括相对于通过双向数据链路在主机设备和客户端设备之间传输的数据信号检测时钟信号的相位。 数据链路包括一个或多个数据线，每个数据线被配置为传送数据信号的相应位。 该相位被编码为客户端相位信息，并通过一个或多个数据线在主机和客户端设备之间传输。 客户端相位信息是在数据链路上的读取和写入操作之间的双向数据链路的电气周转时间周期期间传送的。

公开(公告)号：US20070098163A1

公开(公告)日：2007-05-03

申请号：US11592074

申请日：2006-11-01

申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

IPC分类号： H04N7/167

CPC分类号： G06F11/10

摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于接口上的事务。 基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

公开(公告)号：US20070104327A1

公开(公告)日：2007-05-10

申请号：US11595619

申请日：2006-11-09

申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

IPC分类号： H04N7/167

CPC分类号： H04L1/0045 ,  G06F11/08 ,  G06F11/10 ,  H04L1/0061 ,  H04L2001/0094

摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.

摘要翻译： 描述了用于检测高速非对称接口中的错误的系统和方法。 实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。 第一个组件通过接口的READ和WRITE操作同时从一个接口的一行接收第二个组件的签名。 与从第二组件到第一组件的签名传输相关联的延迟是第二组件计算签名所花费的时间。 所接收的签名与由第一组件存储的签名进行比较。 两个签名对应于特定的READ或WRITE命令。 基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

公开(公告)号：US20070067660A1

公开(公告)日：2007-03-22

申请号：US11231078

申请日：2005-09-19

申请人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

发明人： Stephen Morein ,  Joseph Macri ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

IPC分类号： G06F1/12

CPC分类号： H04L7/02 ,  H04L7/0025 ,  H04L7/0091

摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

摘要翻译： 描述了非对称IO方法和系统。 在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。 共享资源包括一个共享相位内插器。 在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

公开(公告)号：US20070101073A1

公开(公告)日：2007-05-03

申请号：US11359809

申请日：2006-02-22

申请人： Joseph Macri ,  Stephen Morein ,  Ming-Ju Lee ,  Lin Chen

发明人： Joseph Macri ,  Stephen Morein ,  Ming-Ju Lee ,  Lin Chen

IPC分类号： G06F13/00

CPC分类号： G06F12/00 ,  G06F13/4234 ,  G06F13/4243 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

摘要： A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

摘要翻译： 描述了用于执行字节写入的方法和系统，其中字节写入仅涉及仅写入多字节写入操作的特定字节。 实施例包括指示在字节写入操作中要写入哪些字节的掩码数据。 不使用专用的掩码引脚或专用掩码线。 在一个实施例中，掩码数据在数据线上传输，并响应于write_mask命令存储。 在一个实施例中，掩模数据作为写入命令的一部分被发送。

公开(公告)号：US20070038789A1

公开(公告)日：2007-02-15

申请号：US11357291

申请日：2006-02-17

申请人： Joseph Macri ,  Stephen Morein ,  Ming-Ju Lee ,  Lin Chen

发明人： Joseph Macri ,  Stephen Morein ,  Ming-Ju Lee ,  Lin Chen

IPC分类号： G06F13/42

CPC分类号： H04L25/4915 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0814 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0337

摘要： A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.

摘要翻译： 描述了动态总线反演（DBI）方法和系统。 在各种实施例中，发射机通过多比特高速总线向接收机发送数据。 在一个实施例中，发射机基于将要转换到新值的数据比特数来确定是否反转总线。 如果确定总线被反相，则发送器对总线的共享线路上的DBI信号进行编码。 在一个实施例中，共享线路在不同时间用于不同的目的，从而避免了对编码的DBI信号的专用线路或引脚的需要。 接收器接收并解码DBI信号，作为响应，对接收到的数据进行适当的解码。

公开(公告)号：US20070288781A1

公开(公告)日：2007-12-13

申请号：US11732783

申请日：2007-04-03

申请人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

发明人： Joseph Macri ,  Steven Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

摘要： Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.

摘要翻译： 描述用于存储器接口的功耗降低过程的实施例。 电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

公开(公告)号：US20080005455A1

公开(公告)日：2008-01-03

申请号：US11804413

申请日：2007-05-17

申请人： Joseph Macri ,  Steven Morein ,  Ming-Ju Lee ,  Lin Chen

发明人： Joseph Macri ,  Steven Morein ,  Ming-Ju Lee ,  Lin Chen

IPC分类号： G06F12/08 ,  G06F1/12

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2227 ,  Y02D10/14

摘要： Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

摘要翻译： 描述了在模拟定时电路初始化和变得可用的时间段期间继续在低功率模式下工作的存储器件和存储器控制器的实施例。 在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行 模式。 参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由 从低速模式向高速模式的转变将大大降低。

公开(公告)号：US20110063010A1

公开(公告)日：2011-03-17

申请号：US12560991

申请日：2009-09-16

申请人： Jinyung Namkoong ,  Arvind Bomdica ,  Ming-Ju Lee

发明人： Jinyung Namkoong ,  Arvind Bomdica ,  Ming-Ju Lee

IPC分类号： H03L5/00

CPC分类号： H03K19/018528

摘要： A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs.

摘要翻译： 电路包括具有至少两个输入的差分电路，第一可变阻抗电路和第二可变阻抗电路。 第一可变阻抗电路在差分电路的第一分支和输出之间。 第一可变阻抗电路提供第一可变阻抗。 第二可变阻抗电路在差分电路的第二分支和输出之间。 第二可变阻抗电路提供第二可变阻抗。 第一可变阻抗和第二可变阻抗根据两个输入之间的电压差而变化。

公开(公告)号：US07714615B2

公开(公告)日：2010-05-11

申请号：US12032741

申请日：2008-02-18

申请人： Yikai Liang ,  Arvind Bomdica ,  Min Xu ,  Ming-Ju Lee

发明人： Yikai Liang ,  Arvind Bomdica ,  Min Xu ,  Ming-Ju Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/0019 ,  H04L1/08 ,  H04L25/0272 ,  H04L25/0286

摘要： A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.

摘要翻译： 用于去强调通过差分通信链路发送的信息的电路包括电压模式差分电路和双向电流源电路。 电压模式差分电路包括第一和第二输出端子。 电压模式差分电路响应于差分输入电压经由第一输出端经第二输出端提供第一电压和第二电压。 双向电流源电路可操作地耦合在第一和第二端子之间。 双向电流源电路基于第一和第二电压选择性地在第一和第二端子之间的第一和第二方向上提供电流。