公开(公告)号：US07925942B2

公开(公告)日：2011-04-12

申请号：US12539373

申请日：2009-08-11

申请人： Baher S. Haroun ,  Lee D. Whetsel

发明人： Baher S. Haroun ,  Lee D. Whetsel

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G11C29/46

摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

摘要翻译： 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

公开(公告)号：US07915905B2

公开(公告)日：2011-03-29

申请号：US12761544

申请日：2010-04-16

申请人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

发明人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

IPC分类号： G01R31/00

CPC分类号： H03M3/35 ,  H01L22/34 ,  H03M3/43 ,  H03M3/438

摘要： In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.

摘要翻译： 在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。 监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。 如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。 使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。 数字信号以可配置的时间间隔存储以形成数字比特流。 将数字比特流与参考进行比较，以确定失败是否在允许的范围内。

公开(公告)号：US20090265672A1

公开(公告)日：2009-10-22

申请号：US12103961

申请日：2008-04-16

申请人： Ian St.John ,  Mohamed Kamal Mahmoud ,  Baher S. Haroun

发明人： Ian St.John ,  Mohamed Kamal Mahmoud ,  Baher S. Haroun

IPC分类号： G06F17/50

CPC分类号： G06F17/5063

摘要： A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.

摘要翻译： 设计模拟集成电路（IC）的方法，寄生约束分析器和确定模拟IC的布局的方法符合寄生约束。 在一个实施例中，设计模拟IC的方法包括：（1）基于一组规范创建模拟集成电路的示意图，（2）将附加约束附加到原理图，（3）创建模拟 基于包括寄生约束的示意图的集成电路，（4）从布局的寄生元件提取寄生值，以及（5）将所提取的寄生值与寄生约束进行比较以验证其符合性。

公开(公告)号：US20090251164A1

公开(公告)日：2009-10-08

申请号：US12061409

申请日：2008-04-02

申请人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

发明人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

IPC分类号： H01L21/66 ,  H03M3/00

CPC分类号： H03M3/35 ,  H01L22/34 ,  H03M3/43 ,  H03M3/438

摘要： In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.

摘要翻译： 在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。 监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。 如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。 使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。 数字信号以可配置的时间间隔存储以形成数字比特流。 将数字位流与参考值进行比较，以确定缺陷是否在允许范围内。

公开(公告)号：US20090210188A1

公开(公告)日：2009-08-20

申请号：US12434929

申请日：2009-05-04

申请人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

发明人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

IPC分类号： G01R31/28 ,  G06F19/00

CPC分类号： G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

摘要： IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

摘要翻译： IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

公开(公告)号：US06674381B1

公开(公告)日：2004-01-06

申请号：US10377222

申请日：2003-02-28

申请人： Gabriel J. Gomez ,  Baher S. Haroun

发明人： Gabriel J. Gomez ,  Baher S. Haroun

IPC分类号： H03M300

CPC分类号： H03M3/328 ,  H03M3/358 ,  H03M3/424 ,  H03M3/454

摘要： Sigma delta modulators and digital to analog converters therefor are disclosed, in which intentional mismatch is provided in circuit elements of the digital to analog converter to facilitate tone reduction where dynamic element matching is used in selecting the digital to analog converter circuit elements. Methods are disclosed for fabricating digital to analog converters for providing analog feedback using a group of circuit elements selected according to a quantized output signal in a sigma delta modulator, in which a plurality of matched circuit elements having values within a tolerance amount of a design value are provided in the group along with at least one mismatched circuit element having a mismatched element value differing from the design value by a mismatch amount, where the mismatch amount is greater than the tolerance amount.

摘要翻译： 公开了Sigma delta调制器及其数模转换器，其中在数模转换器的电路元件中提供有意的失配，以便于在选择数模转换器电路元件时使用动态元件匹配来进行音调降低。 公开了用于制造数模转换器的方法，用于使用在Σ-Δ调制器中根据量化输出信号选择的一组电路元件提供模拟反馈，其中多个匹配电路元件具有在设计值的容许量内 在组中连同至少一个具有与设计值不同的不匹配元件值的错配电路元件与不匹配量一起提供，其中失配量大于容许量。

公开(公告)号：US20130241663A1

公开(公告)日：2013-09-19

申请号：US13421567

申请日：2012-03-15

申请人： Lei Ding ,  Rahmi Hezar ,  Joonhoi Hur ,  Baher S. Haroun

发明人： Lei Ding ,  Rahmi Hezar ,  Joonhoi Hur ,  Baher S. Haroun

IPC分类号： H03K7/08

CPC分类号： H03K7/08

摘要： A method is provided. An input signal is received, and a noise-shaped signal is generated from the input signal. The noise-shaped signal is formed from a plurality of noise-shaping levels. A pulse stream is generated from the noise-shaped signal over a plurality of periods, where each period has a plurality of frames. The pulse stream also includes a plurality of pulse sets, where each pulse set is associated with at least one of the noise-shaping levels, and, for each pulse set having a total pulse width for its period that is less than its period and greater than zero, each pulse set includes at least one pulse in each frame for its period.

摘要翻译： 提供了一种方法。 接收输入信号，并从输入信号产生噪声信号。 噪声形状信号由多个噪声整形电平形成。 在多个周期中，从噪声信号产生脉冲流，其中每个周期具有多个帧。 脉冲流还包括多个脉冲组，其中每个脉冲组与噪声整形电平中的至少一个相关联，并且对于每个具有小于其周期和更大周期的总脉冲宽度的脉冲集合 每个脉冲组在其周期中包括每帧中的至少一个脉冲。

公开(公告)号：US20130120186A1

公开(公告)日：2013-05-16

申请号：US13295885

申请日：2011-11-14

申请人： Vijay B. Rentala ,  Srinath M. Ramaswamy ,  Brian P. Ginsburg ,  Eunyoung Seok ,  Baher S. Haroun

发明人： Vijay B. Rentala ,  Srinath M. Ramaswamy ,  Brian P. Ginsburg ,  Eunyoung Seok ,  Baher S. Haroun

IPC分类号： G01S13/00 ,  H03L7/085

CPC分类号： G01S13/00 ,  G01S13/08 ,  H03K2005/00071 ,  H03L7/0812 ,  H03L7/0891

摘要： A method for providing a plurality of narrow pulses is provided. A first pulse having a first width is received by a delay line having a plurality of delay cells. This first pulse has a first width. In response to this first pulse, a plurality of second pulses is generated by the delay line, where each second pulse has a second width that is less than the first width. First and second delay pulses are also generated by the delay line, and a delay for each delay cell in the delay line can then be adjusted if a rising edge of the second delay pulse is misaligned with a falling edge of the first delay pulse.

摘要翻译： 提供了一种用于提供多个窄脉冲的方法。 具有第一宽度的第一脉冲由具有多个延迟单元的延迟线接收。 该第一脉冲具有第一宽度。 响应于该第一脉冲，延迟线产生多个第二脉冲，其中每个第二脉冲具有小于第一宽度的第二宽度。 第一延迟脉冲和第二延迟脉冲也由延迟线产生，并且如果第二延迟脉冲的上升沿与第一延迟脉冲的下降沿不一致，则可延迟延迟线中的每个延迟单元的延迟。

公开(公告)号：US20130099824A1

公开(公告)日：2013-04-25

申请号：US13281227

申请日：2011-10-25

申请人： Robert F. Payne ,  Baher S. Haroun

发明人： Robert F. Payne ,  Baher S. Haroun

IPC分类号： H03K5/22

CPC分类号： H03K5/2481

摘要： An apparatus is provided. The apparatus comprises backend circuitry and pairs of redundant input circuits. Each pair of redundant input circuits is configured to form a differential pair of transistors, and each redundant input circuit includes a multiplexer and a set of transistors. The multiplexer is coupled to the backend circuitry, and each transistor from the set of transistors has a first passive electrode, a second passive electrode, and a control electrode. The first passive electrode of each transistor from the set of transistors is coupled to the multiplexer, and the control electrodes from the set of transistors are coupled together.

摘要翻译： 提供了一种装置。 该装置包括后端电路和冗余输入电路对。 每对冗余输入电路被配置为形成差分对晶体管，并且每个冗余输入电路包括多路复用器和一组晶体管。 多路复用器耦合到后端电路，并且来自该组晶体管的每个晶体管具有第一无源电极，第二无源电极和控制电极。 来自晶体管组的每个晶体管的第一无源电极耦合到多路复用器，并且来自该组晶体管的控制电极耦合在一起。

公开(公告)号：US20120096325A1

公开(公告)日：2012-04-19

申请号：US13330178

申请日：2011-12-19

申请人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

发明人： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Kinra

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

摘要： Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

摘要翻译： 测试访问端口（TAP）可以在IC和知识产权核心设计级别使用。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。