公开(公告)号：US07919379B2

公开(公告)日：2011-04-05

申请号：US11852906

申请日：2007-09-10

申请人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

发明人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

IPC分类号： H01L21/00 ,  H01L21/336

CPC分类号： H01L21/31116 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

摘要翻译： 本发明涉及半导体器件，更具体地说，涉及一种基本上不去除半导体衬底去除对半导体衬底的表面有选择性的介电隔离层的工艺和结构。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括在半导体衬底上形成场效应晶体管，所述FET包括电介质间隔物和所述栅极结构，所述电介质隔离物邻近所述栅极结构的侧壁并位于所述半导体衬底中的源极/漏极区域上; 在FET上沉积第一氮化物层; 并且基本上不去除半导体衬底，去除对半导体衬底的选择性的氮化物层和电介质衬垫。

公开(公告)号：US07678634B2

公开(公告)日：2010-03-16

申请号：US12020916

申请日：2008-01-28

申请人： Qiqing Ouyang ,  Kathryn T. Schonenberg

发明人： Qiqing Ouyang ,  Kathryn T. Schonenberg

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： A first dielectric layer is formed over a PFET gate and an NFET gate, and lithographically patterned to expose a PFET area, while covering an NFET area. Exposed PFET active area is etched and refilled with a SiGe alloy, which applies a uniaxial compressive stress to a PFET channel. A second dielectric layer is formed over the PFET gate and the NFET gate, and lithographically patterned to expose the NFET area, while covering the PFET area. Exposed NFET active area is etched and refilled with a silicon-carbon alloy, which applies a uniaxial tensile stress to an NFET channel. Dopants may be introduced into the SiGe and silicon-carbon regions by in-situ doping or by ion implantation.

摘要翻译： 在PFET栅极和NFET栅极上形成第一电介质层，并且被光刻图案化以在覆盖NFET区域的同时暴露PFET区域。 暴露的PFET有源区被蚀刻并用SiGe合金重新填充，SiGe合金向PFET通道施加单轴压应力。 第二电介质层形成在PFET栅极和NFET栅极上，并且被光刻图案化以暴露NFET区域，同时覆盖PFET区域。 暴露的NFET有源区被蚀刻并用硅 - 碳合金重新填充，硅 - 碳合金对NFET通道施加单轴拉伸应力。 可以通过原位掺杂或通过离子注入将掺杂剂引入到SiGe和硅 - 碳区域中。

公开(公告)号：US20090081836A1

公开(公告)日：2009-03-26

申请号：US11860127

申请日：2007-09-24

申请人： Yaocheng Liu ,  Qiqing C. Ouyang ,  Kathryn T. Schonenberg ,  Chun-Yung Sung

发明人： Yaocheng Liu ,  Qiqing C. Ouyang ,  Kathryn T. Schonenberg ,  Chun-Yung Sung

IPC分类号： H01L21/265 ,  H01L21/8238

CPC分类号： H01L21/26506 ,  H01L21/268 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

摘要： A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.

摘要翻译： 提供了在源极和漏极区域中形成晶体Si：C的方法。 在形成浅沟槽隔离和场效应晶体管的栅电极之后，在栅电极上形成栅极间隔物。 在源极和漏极区域中进行前置放电，随后进行碳注入。 源区和漏区的上部包括硅，锗和/或碳的无定形混合物。 沉积抗反射层以增强激光束到硅衬底中的吸收。 激光束在包括具有无定形混合物的上源极和漏极区域的硅衬底上扫描。 控制激光束的能量使得半导体衬底的温度高于无定形混合物的熔融温度但低于氧化硅的玻璃化转变温度，从而保持了半导体结构的结构完整性。

公开(公告)号：US20090065817A1

公开(公告)日：2009-03-12

申请号：US11852906

申请日：2007-09-10

申请人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

发明人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

IPC分类号： H01L21/311 ,  H01L29/78

CPC分类号： H01L21/31116 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

摘要翻译： 本发明涉及半导体器件，更具体地说，涉及一种基本上不去除半导体衬底去除对半导体衬底的表面有选择性的介电隔离层的工艺和结构。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括在半导体衬底上形成场效应晶体管，所述FET包括电介质间隔物和所述栅极结构，所述电介质隔离物邻近所述栅极结构的侧壁并位于所述半导体衬底中的源极/漏极区域上; 在所述FET上沉积第一氮化物层; 并且基本上不去除半导体衬底，去除对半导体衬底的选择性的氮化物层和电介质衬垫。

公开(公告)号：US20080265282A1

公开(公告)日：2008-10-30

申请号：US11741836

申请日：2007-04-30

申请人： Oleg Gluschenkov ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

发明人： Oleg Gluschenkov ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

IPC分类号： H01L31/11 ,  H01L21/331 ,  H01L31/117 ,  H01L31/00

CPC分类号： H01L29/66242 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

摘要： Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

摘要翻译： 公开了一种改进的半导体结构（例如，硅锗（SiGe）异质结双极晶体管），其具有窄的基本上无间隙的SIC基座，其外部基极具有最小的重叠。 此外，公开了一种形成晶体管的方法，该晶体管使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本无间隙的集电极。 因此，所得到的SiGe HBT晶体管可以用比传统技术可以实现的更窄的基极和集电极空间电荷区域来制造。

公开(公告)号：US20080128861A1

公开(公告)日：2008-06-05

申请号：US11555906

申请日：2006-11-02

申请人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

发明人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

IPC分类号： H01L29/73

CPC分类号： H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.

摘要翻译： 提供双极晶体管，特别是SiGe异质结双极晶体管的性能的方法与通过本发明方法形成的结构一起提供。 所述方法包括向至少一个收集器提供包含C，惰性气体或其混合物的富含物质的掺杂剂区域。 富含物质的掺杂剂区域围绕收集器的中心部分形成周边或环形掺杂剂区域。 然后将第一导电型掺杂剂注入到集电极的中心部分中，以形成由外部富物质掺杂区域横向约束，即限制的第一导电型掺杂剂区域。

公开(公告)号：US20080083955A1

公开(公告)日：2008-04-10

申请号：US11538506

申请日：2006-10-04

申请人： Thomas S. Kanarsky ,  Qiqing Ouyang ,  Kathryn T. Schonenberg ,  Chun-Yung Sung

发明人： Thomas S. Kanarsky ,  Qiqing Ouyang ,  Kathryn T. Schonenberg ,  Chun-Yung Sung

IPC分类号： H01L29/76

CPC分类号： H01L29/7833 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76841 ,  H01L21/76865 ,  H01L29/7843 ,  H01L29/7845

摘要： A stressed liner for improving carrier mobility in a transistor and a method for fabricating the same is disclosed. The stressed liner includes an intrinsically stressed conductive film encapsulated between two insulating layers such as silicon nitride, silicon oxide, or oxynitride. The stressed liner may be compressively-stressed or tensile-stressed depending on whether an n-FET or p-FET is required.

摘要翻译： 公开了一种用于改善晶体管中的载流子迁移率的应力衬垫及其制造方法。 应力衬里包括密封在两个绝缘层（例如氮化硅，氧化硅或氮氧化物）之间的本征应力导电膜。 根据是否需要n-FET或p-FET，应力衬垫可以是压应力或拉伸应力。

公开(公告)号：US06780695B1

公开(公告)日：2004-08-24

申请号：US10249563

申请日：2003-04-18

申请人： Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

发明人： Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

IPC分类号： H01L218238

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.

摘要翻译： 提供一种形成具有凸起的外在基极的BiCMOS集成电路的方法。 该方法包括首先在位于具有用于形成至少一个双极晶体管的器件区域的衬底的顶部的栅极电介质的表面上方形成多晶硅层，以及用于形成至少一个互补金属氧化物半导体（CMOS）晶体管的器件区域）。 然后将多晶硅层图案化以在器件区域上提供用于形成至少一个双极晶体管及其周围区域的牺牲多晶硅层，同时在用于形成至少一个CMOS晶体管的器件区域中提供至少一个栅极导体。 然后围绕至少一个栅极导体的每一个形成至少一对间隔物，然后选择性地去除双极器件区域上的牺牲多晶硅层的一部分以在双极器件区域中提供至少一个开口。 然后在至少一个开口中形成至少一个具有凸起的非本征基极的双极晶体管。