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公开(公告)号：US20080083955A1
公开(公告)日：2008-04-10
申请号：US11538506
申请日：2006-10-04
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L21/76829 , H01L21/76831 , H01L21/76841 , H01L21/76865 , H01L29/7843 , H01L29/7845
摘要： A stressed liner for improving carrier mobility in a transistor and a method for fabricating the same is disclosed. The stressed liner includes an intrinsically stressed conductive film encapsulated between two insulating layers such as silicon nitride, silicon oxide, or oxynitride. The stressed liner may be compressively-stressed or tensile-stressed depending on whether an n-FET or p-FET is required.
摘要翻译： 公开了一种用于改善晶体管中的载流子迁移率的应力衬垫及其制造方法。 应力衬里包括密封在两个绝缘层（例如氮化硅，氧化硅或氮氧化物）之间的本征应力导电膜。 根据是否需要n-FET或p-FET，应力衬垫可以是压应力或拉伸应力。
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公开(公告)号：US20090191679A1
公开(公告)日：2009-07-30
申请号：US12020916
申请日：2008-01-28
IPC分类号： H01L21/8236
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： A first dielectric layer is formed over a PFET gate and an NFET gate, and lithographically patterned to expose a PFET area, while covering an NFET area. Exposed PFET active area is etched and refilled with a SiGe alloy, which applies a uniaxial compressive stress to a PFET channel. A second dielectric layer is formed over the PFET gate and the NFET gate, and lithographically patterned to expose the NFET area, while covering the PFET area. Exposed NFET active area is etched and refilled with a silicon-carbon alloy, which applies a uniaxial tensile stress to an NFET channel. Dopants may be introduced into the SiGe and silicon-carbon regions by in-situ doping or by ion implantation.
摘要翻译： 在PFET栅极和NFET栅极上形成第一电介质层，并且被光刻图案化以在覆盖NFET区域的同时暴露PFET区域。 暴露的PFET有源区被蚀刻并用SiGe合金重新填充，SiGe合金向PFET通道施加单轴压应力。 第二电介质层形成在PFET栅极和NFET栅极上，并且被光刻图案化以暴露NFET区域，同时覆盖PFET区域。 暴露的NFET有源区被蚀刻并用硅 - 碳合金重新填充，硅 - 碳合金对NFET通道施加单轴拉伸应力。 可以通过原位掺杂或通过离子注入将掺杂剂引入到SiGe和硅 - 碳区域中。
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公开(公告)号：US20090174002A1
公开(公告)日：2009-07-09
申请号：US11971437
申请日：2008-01-09
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： Source and drain extension regions are selectively removed by a dopant concentration dependent etch or a doping type dependent etch, and an embedded stress-generating material such as SiGe alloy or a Si:C alloy in the source and drain extension regions is grown on a semiconductor substrate. The embedded stress-generating material may be grown only in the source and drain extension regions, or in the source and drain extension regions and in deep source and drain regions. In one embodiment, an etch process that removes doped semiconductor regions of one conductivity type selective to doped semiconductor regions of another conductivity type may be employed. In another embodiment, a dopant concentration dependent etch process that removes doped semiconductor regions irrespective of the conductivity type selective to undoped semiconductor regions may be employed.
摘要翻译： 源极和漏极延伸区域通过掺杂剂浓度依赖性蚀刻或掺杂型依赖性蚀刻被选择性去除，并且在源极和漏极延伸区域中嵌入的应力产生材料如SiGe合金或Si：C合金生长在半导体 基质。 嵌入的应力产生材料可以仅在源极和漏极延伸区域中，或者在源极和漏极延伸区域以及深的源极和漏极区域中生长。 在一个实施例中，可以采用去除对另一种导电类型的掺杂半导体区域有选择性的一种导电类型的掺杂半导体区域的蚀刻工艺。 在另一个实施例中，可以采用去除掺杂半导体区域而不考虑对未掺杂的半导体区域有选择性的导电类型的掺杂浓度依赖蚀刻工艺。
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公开(公告)号：US07678634B2
公开(公告)日：2010-03-16
申请号：US12020916
申请日：2008-01-28
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： A first dielectric layer is formed over a PFET gate and an NFET gate, and lithographically patterned to expose a PFET area, while covering an NFET area. Exposed PFET active area is etched and refilled with a SiGe alloy, which applies a uniaxial compressive stress to a PFET channel. A second dielectric layer is formed over the PFET gate and the NFET gate, and lithographically patterned to expose the NFET area, while covering the PFET area. Exposed NFET active area is etched and refilled with a silicon-carbon alloy, which applies a uniaxial tensile stress to an NFET channel. Dopants may be introduced into the SiGe and silicon-carbon regions by in-situ doping or by ion implantation.
摘要翻译： 在PFET栅极和NFET栅极上形成第一电介质层，并且被光刻图案化以在覆盖NFET区域的同时暴露PFET区域。 暴露的PFET有源区被蚀刻并用SiGe合金重新填充，SiGe合金向PFET通道施加单轴压应力。 第二电介质层形成在PFET栅极和NFET栅极上，并且被光刻图案化以暴露NFET区域，同时覆盖PFET区域。 暴露的NFET有源区被蚀刻并用硅 - 碳合金重新填充，硅 - 碳合金对NFET通道施加单轴拉伸应力。 可以通过原位掺杂或通过离子注入将掺杂剂引入到SiGe和硅 - 碳区域中。
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5.发明授权Method of forming CMOS with Si:C source/drain by laser melting and recrystallization 有权通过激光熔融和重结晶用Si：C源极/漏极形成CMOS的方法公开(公告)号：US07598147B2
公开(公告)日：2009-10-06
申请号：US11860127
申请日：2007-09-24
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/66545 , H01L29/7848
摘要： A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.
摘要翻译： 提供了在源极和漏极区域中形成晶体Si：C的方法。 在形成浅沟槽隔离和场效应晶体管的栅电极之后，在栅电极上形成栅极间隔物。 在源极和漏极区域中进行前置放电，随后进行碳注入。 源区和漏区的上部包括硅，锗和/或碳的无定形混合物。 沉积抗反射层以增强激光束到硅衬底中的吸收。 激光束在包括具有无定形混合物的上源极和漏极区域的硅衬底上扫描。 控制激光束的能量使得半导体衬底的温度高于无定形混合物的熔融温度但低于氧化硅的玻璃化转变温度，从而保持半导体结构的结构完整性。
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6.发明申请METHOD OF FORMING CMOS WITH SI:C SOURCE/DRAIN BY LASER MELTING AND RECRYSTALLIZATION 有权通过激光熔化和重结晶形成CMOS与Si：C源/漏极的方法公开(公告)号：US20090081836A1
公开(公告)日：2009-03-26
申请号：US11860127
申请日：2007-09-24
IPC分类号： H01L21/265 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/268 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/66545 , H01L29/7848
摘要： A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.
摘要翻译： 提供了在源极和漏极区域中形成晶体Si：C的方法。 在形成浅沟槽隔离和场效应晶体管的栅电极之后，在栅电极上形成栅极间隔物。 在源极和漏极区域中进行前置放电，随后进行碳注入。 源区和漏区的上部包括硅，锗和/或碳的无定形混合物。 沉积抗反射层以增强激光束到硅衬底中的吸收。 激光束在包括具有无定形混合物的上源极和漏极区域的硅衬底上扫描。 控制激光束的能量使得半导体衬底的温度高于无定形混合物的熔融温度但低于氧化硅的玻璃化转变温度，从而保持了半导体结构的结构完整性。
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公开(公告)号：US07955926B2
公开(公告)日：2011-06-07
申请号：US12055682
申请日：2008-03-26
IPC分类号： H01L21/00
CPC分类号： H01L21/76224 , H01L21/28123 , H01L29/517
摘要： In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.
摘要翻译： 在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质，其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。
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公开(公告)号：US07900167B2
公开(公告)日：2011-03-01
申请号：US11923131
申请日：2007-10-24
IPC分类号： G06F17/50
CPC分类号： H01L29/7371 , H01L29/0826 , H01L29/161
摘要： Disclosed is a design structure for an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
摘要翻译： 公开了具有窄的基本上无间隙的SIC基座的改进的半导体结构（例如，硅锗（SiGe）异质结双极晶体管）的设计结构，其具有极小的外部基极的重叠。 此外，公开了一种形成晶体管的方法，该晶体管使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本无间隙的集电极。 因此，所得到的SiGe HBT晶体管可以用比传统技术可以实现的更窄的基极和集电极空间电荷区域来制造。
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公开(公告)号：US07682917B2
公开(公告)日：2010-03-23
申请号：US12016326
申请日：2008-01-18
申请人： Stephen W. Bedell , Michael Chudzik , William K. Henson , Naim Moumen , Vijay Narayanan , Devendra K. Sadana , Kathryn T. Schonenberg , Ghavam Shahidi
发明人： Stephen W. Bedell , Michael Chudzik , William K. Henson , Naim Moumen , Vijay Narayanan , Devendra K. Sadana , Kathryn T. Schonenberg , Ghavam Shahidi
IPC分类号： H01L21/336
CPC分类号： H01L29/7847 , H01L21/324 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high reactivity with oxygen. The disposable gate spacer absorbs any oxygen during subsequent high temperature processing such as a stress memorization anneal. A metal is deposited over, and reacted with, the gate electrode and source and drain regions to form metal semiconductor alloy regions. The disposable gate spacer is subsequently removed selective to the metal semiconductor alloy regions. A porous or non-porous low-k dielectric material is deposited to provide a low parasitic capacitance between the gate electrode and the source and drain regions. The gate dielectric maintains the original dielectric constant since the disposable gate spacer prevents absorption of additional oxygen during high temperature processes.
摘要翻译： 一次性间隔物直接形成在栅极电极和栅极电介质的侧壁上或紧邻栅电极的侧壁上。 一次性间隔件包括清除氧的材料，例如金属，金属氮化物或具有高氧反应性的半导体材料。 一次性栅极间隔件在随后的高温处理例如应力记忆退火期间吸收任何氧气。 将金属沉积在栅电极和源极和漏极区上并与其反应以形成金属半导体合金区域。 一次性栅极间隔物随后被选择性地移除到金属半导体合金区域。 沉积多孔或非多孔低k电介质材料以在栅极电极和源极和漏极区域之间提供低的寄生电容。 栅极电介质保持原始介电常数，因为一次性栅极间隔物可防止在高温过程中吸收额外的氧。
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公开(公告)号：US20090108300A1
公开(公告)日：2009-04-30
申请号：US11923131
申请日：2007-10-24
IPC分类号： H01L29/737
CPC分类号： H01L29/7371 , H01L29/0826 , H01L29/161
摘要： Disclosed is a design structure for an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
摘要翻译： 公开了具有窄的基本上无间隙的SIC基座的改进的半导体结构（例如，硅锗（SiGe）异质结双极晶体管）的设计结构，其具有极小的外部基极的重叠。 此外，公开了一种形成晶体管的方法，该晶体管使用与SIC基座的快速热退火相反的激光退火以产生窄SIC基座和基本无间隙的集电极。 因此，所得到的SiGe HBT晶体管可以用比传统技术可以实现的更窄的基极和集电极空间电荷区域来制造。
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