公开(公告)号：US06959016B1

公开(公告)日：2005-10-25

申请号：US09633552

申请日：2000-08-07

申请人： Brent Keeth ,  Troy A. Manning

发明人： Brent Keeth ,  Troy A. Manning

IPC分类号： G06F1/10 ,  G11C7/22 ,  H03K5/13 ,  H03L7/07 ,  H03L7/081 ,  H04J3/06

CPC分类号： G06F1/10 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229 ,  H03K5/131 ,  H03L7/07 ,  H03L7/0812

摘要： A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the timing of a digital signal in relatively large phase increments. The delayed clock signal is used to clock a register to which the digital signal is applied to control the timing a the digital signal clocked through the register responsive to adjusting the timing of the fine delay circuit and the coarse delay circuit. The timing relationship is initially adjusted by altering the delay of the fine delay circuit. Whenever the maximum or minimum delay of the fine delay circuit is reached, the coarse delay circuit is adjusted. The variable delay circuit may be used in a memory device to control the timing at which read data is applied to the data bus of the memory device. The fine delay circuit includes a multi—tapped delay line coupled to a multiplexer that selects one of the taps for use in generating the delayed clock. When the first or last tap is selected, the timing of the coarse delay circuit is adjusted. The coarse delay circuit includes a counter that generates the digital signal upon counting from an initial count to the terminal count. The coarse delay circuit is adjusted by adjusting the initial count of the counter.

摘要翻译： 可变延迟电路由精细延迟电路和粗略延迟电路构成。 精细延迟电路相对于输入时钟信号以相对小的相位增量调整延迟时钟信号的延迟。 粗延迟电路以相对大的相位增量来调整数字信号的定时。 延迟时钟信号用于对应用数字信号的寄存器进行时钟，以响应于调整精细延迟电路和粗略延迟电路的定时来控制通过寄存器定时的数字信号的定时。 最初通过改变精细延迟电路的延迟来调整定时关系。 每当达到精细延迟电路的最大或最小延迟时，调整粗略延迟电路。 可变延迟电路可以用于存储器件中以控制将读取数据应用于存储器件的数据总线的定时。 精细延迟电路包括耦合到多路复用器的多抽头延迟线，其选择一个抽头用于产生延迟的时钟。 当选择第一或最后一个抽头时，调整粗延迟电路的定时。 粗延迟电路包括从初始计数到终端计数的计数时产生数字信号的计数器。 通过调整计数器的初始计数来调整粗略延迟电路。

公开(公告)号：US06256255B1

公开(公告)日：2001-07-03

申请号：US09617317

申请日：2000-07-17

申请人： Brent Keeth ,  Troy A. Manning

发明人： Brent Keeth ,  Troy A. Manning

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C7/1006

摘要： A multi-bank memory includes memory cells arranged in individually selectable banks that share column select signals. The memory cells are addressed by a row decoder that activates word lines to couple data onto digit lines. The digit lines are coupled to input/output lines through first and second series-connected switches. The first switches are input/output switches that are controlled by column select signals that are shared between multiple banks. The second switches are bank select switches that are controlled by a bank decoder, for coupling only one of the banks to input/output lines and isolating the other banks from input/output lines. The invention reduces timing requirements between operations in different banks, and allows concurrent operations in different banks, thereby increasing the speed at which the memory operates.

摘要翻译： 多存储体存储器包括布置在单独可选择的存储体中的存储单元，其共享列选择信号。 存储器单元由行解码器寻址，其激活字线以将数据耦合到数字线上。 数字线通过第一和第二串联连接的开关耦合到输入/输出线。 第一个开关是由多个存储体之间共享的列选择信号控制的输入/输出开关。 第二开关是由银行解码器控制的存储体选择开关，用于仅将一个存储体耦合到输入/输出线路，并将其它存储体与输入/输出线路隔离。 本发明减少了不同库中的操作之间的时序要求，并且允许在不同的存储体中进行并行操作，从而增加存储器操作的速度。

公开(公告)号：US6167495A

公开(公告)日：2000-12-26

申请号：US141467

申请日：1998-08-27

申请人： Brent Keeth ,  Troy A. Manning

发明人： Brent Keeth ,  Troy A. Manning

IPC分类号： G11C7/10 ,  G11C7/20 ,  G06F12/16

CPC分类号： G11C7/1072 ,  G11C7/20

摘要： A system for detecting an initialization flag signal and distinguishing it from a normal flag signal having half the duration of the initialization flag signal. The initialization flag detection system may be included in the command buffer of a packetized DRAM that is used in a computer system. In one embodiment, the initialization flag detection system includes a pair of shift registers receiving the flag signal at their respective data inputs. One of the shift registers is clocked by a signal corresponding to an externally applied to command clock signal, while the other shift register is clocked by a quadrature clock signal. Together, the shift registers store a number of samples taken over a duration that is longer than the duration of the normal flag signal. The outputs of the shift registers are applied to a logic circuit, such as a NAND gate, that generates an initialization signal when all of the samples stored in the shift registers correspond to the logic levels of the flag signal. In another embodiment, the initialization flag detection system includes a plurality of latches receiving the flag signals at their data inputs. The latches are clocked by respective strobe signals corresponding to the command clock signal, but having phases that differ from each other. The outputs of the latches are applied to a logic circuit, such as a NAND) gate. Finally, in another embodiment of the invention, the bits of the command packet are sampled along with the flag signal and compared to the samples of the flag signal to detect when a command packet having a predetermined pattern does not correspond to a flag signal having a predetermined pattern.

摘要翻译： 用于检测初始化标志信号并将其与具有初始化标志信号的持续时间的一半的正常标志信号区分开的系统。 初始化标志检测系统可以包括在计算机系统中使用的分组化DRAM的命令缓冲器中。 在一个实施例中，初始化标志检测系统包括在它们各自的数据输入端接收标志信号的一对移位寄存器。 一个移位寄存器由对应于外部施加到命令时钟信号的信号计时，而另一个移位寄存器由正交时钟信号计时。 移位寄存器一起存储长于正常标志信号的持续时间的持续时间的采样数量。 当存储在移位寄存器中的所有采样都对应于标志信号的逻辑电平时，移位寄存器的输出被施加到逻辑电路，例如与非门，其产生初始化信号。 在另一个实施例中，初始化标志检测系统包括在其数据输入端接收标志信号的多个锁存器。 锁存器由对应于命令时钟信号的相应选通信号计时，但具有彼此不同的相位。 锁存器的输出被施加到逻辑电路，例如NAND门）。 最后，在本发明的另一个实施例中，命令分组的比特与标志信号一起被采样，并与标志信号的样本进行比较，以检测何时具有预定模式的命令分组不对应于具有 预定模式。

公开(公告)号：US6122217A

公开(公告)日：2000-09-19

申请号：US244573

申请日：1999-02-04

申请人： Brent Keeth ,  Troy A. Manning

发明人： Brent Keeth ,  Troy A. Manning

IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C7/1006

摘要： A multi-bank memory includes memory cells arranged in individually selectable banks that share column select signals. The memory cells are addressed by a row decoder that activates word lines to couple data onto digit lines. The digit lines are coupled to input/output lines through first and second series-connected switches. The first switches are input/output switches that are controlled by column select signals that are shared between multiple banks. The second switches are bank select switches that are controlled by a bank decoder, for coupling only one of the banks to input/output lines and isolating the other banks from input/output lines. The invention reduces timing requirements between operations in different banks, and allows concurrent operations in different banks, thereby increasing the speed at which the memory operates.

摘要翻译： 多存储体存储器包括布置在单独可选择的存储体中的存储单元，其共享列选择信号。 存储器单元由行解码器寻址，其激活字线以将数据耦合到数字线上。 数字线通过第一和第二串联连接的开关耦合到输入/输出线。 第一个开关是由多个银行之间共享的列选择信号控制的输入/输出开关。 第二开关是由银行解码器控制的存储体选择开关，用于仅将一个存储体耦合到输入/输出线路，并将其它存储体与输入/输出线路隔离。 本发明减少了不同库中的操作之间的时序要求，并且允许在不同的存储体中进行并行操作，从而增加存储器操作的速度。

公开(公告)号：US5935263A

公开(公告)日：1999-08-10

申请号：US886195

申请日：1997-07-01

申请人： Brent Keeth ,  Troy A. Manning ,  Chris G. Martin ,  Kim M. Pierce ,  Wallace E. Fister ,  Kevin J. Ryan ,  Terry R. Lee ,  Mike Pearson ,  Thomas W. Voshell

发明人： Brent Keeth ,  Troy A. Manning ,  Chris G. Martin ,  Kim M. Pierce ,  Wallace E. Fister ,  Kevin J. Ryan ,  Terry R. Lee ,  Mike Pearson ,  Thomas W. Voshell

IPC分类号： G11C29/38 ,  G11C29/48 ,  H03M13/09 ,  G06F11/00

CPC分类号： H03M13/093 ,  G11C29/38 ,  G11C29/48

摘要： A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.

摘要翻译： 存储器件包括将数据从耦合到存储器阵列的I / O电路传送到输出三态缓冲器的输出数据路径。 比较电路将来自I / O电路的数据与期望的数据模式进行比较。 如果数据与所需模式不匹配，则比较电路输出输入到输出缓冲器的错误信号。 当输出缓冲器接收到错误信号时，输出缓冲器被禁止，并在数据总线上输出三态条件。 由于误差信号对应于多个数据位，所以输出缓冲器的三态条件保持数据时钟的多于一个刻度，而不是仅一个刻度。 因此，三态条件保持在总线上足够长，使得测试系统即使在非常高的时钟频率也可以检测三态条件。

公开(公告)号：US07813194B2

公开(公告)日：2010-10-12

申请号：US12372331

申请日：2009-02-17

申请人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

发明人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G11C29/00 ,  G11C7/06

CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

摘要翻译： 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

公开(公告)号：US20100085825A1

公开(公告)日：2010-04-08

申请号：US12246882

申请日：2008-10-07

申请人： Brent Keeth ,  Chris G. Martin ,  Troy A. Manning ,  Joe M. Jeddeloh ,  Timothy B. Cowles ,  Jim Rehmeyer ,  Paul A. LaBerge

发明人： Brent Keeth ,  Chris G. Martin ,  Troy A. Manning ,  Joe M. Jeddeloh ,  Timothy B. Cowles ,  Jim Rehmeyer ,  Paul A. LaBerge

IPC分类号： G11C29/04 ,  G11C8/00

CPC分类号： G06F12/08 ,  G06F12/10 ,  G11C5/025 ,  G11C29/04 ,  G11C29/18 ,  G11C29/76 ,  G11C29/78 ,  G11C29/808 ,  G11C29/812 ,  G11C29/883 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.

摘要翻译： 各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。

公开(公告)号：US20090147600A1

公开(公告)日：2009-06-11

申请号：US12372331

申请日：2009-02-17

申请人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

发明人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G11C29/00 ,  G11C17/16

CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

摘要翻译： 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

公开(公告)号：US07408825B2

公开(公告)日：2008-08-05

申请号：US11714979

申请日：2007-03-07

申请人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

发明人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G11C7/00

CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

摘要翻译： 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

公开(公告)号：US07215586B2

公开(公告)日：2007-05-08

申请号：US11170260

申请日：2005-06-29

申请人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

发明人： Chris G. Martin ,  Troy A. Manning ,  Brent Keeth

IPC分类号： G11C7/00

CPC分类号： G11C17/165 ,  G11C29/4401 ,  G11C29/789 ,  G11C29/802 ,  G11C29/808 ,  G11C2029/4402

摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

摘要翻译： 用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。 第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。 修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。 当第一存储器访问对应于第一缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。