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    DOUBLE-GATE FETs (FIELD EFFECT TRANSISTORS)
    41.
    发明申请
    DOUBLE-GATE FETs (FIELD EFFECT TRANSISTORS) 失效
    双栅FET（场效应晶体管）

    公开(公告)号：US20060172496A1

    公开(公告)日：2006-08-03

    申请号：US10905979

    申请日：2005-01-28

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/78654

    摘要： A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.

    摘要翻译： 一种用于形成具有相互对准的双栅极的晶体管的方法。 该方法包括以下步骤：（a）提供环绕栅极晶体管结构，其中环绕栅极晶体管结构包括（i）半导体区域和（ii）围绕半导体区域包围的栅电极区域，其中 栅电极区域通过栅极电介质膜与半导体区域电绝缘; 以及（b）去除环绕栅极晶体管结构的第一和第二部分，以便从栅极电极区域形成顶部和底部栅电极，其中顶部和底部栅电极彼此电断开。

    METHODS OF FABRICATING VERTICAL CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR ARRANGEMENT IN ARRAYS AND FIELD EFFECT TRANSISTORS AND ARRAYS FORMED THEREBY
    44.
    发明申请
    METHODS OF FABRICATING VERTICAL CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR ARRANGEMENT IN ARRAYS AND FIELD EFFECT TRANSISTORS AND ARRAYS FORMED THEREBY 有权
    制备垂直碳纳米管场效应晶体管的方法在阵列和场效应晶体管中的布置及其形成的阵列

    公开(公告)号：US20080044954A1

    公开(公告)日：2008-02-21

    申请号：US11926627

    申请日：2007-10-29

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

    IPC分类号： H01L21/8234

    CPC分类号： H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

    摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

    摘要翻译： 一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。 所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。 栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。

    SEMICONDUCTOR TRANSISTORS WITH CONTACT HOLES CLOSE TO GATES
    46.
    发明申请
    SEMICONDUCTOR TRANSISTORS WITH CONTACT HOLES CLOSE TO GATES 有权
    具有接触孔的半导体晶体管靠近门

    公开(公告)号：US20070102766A1

    公开(公告)日：2007-05-10

    申请号：US11163966

    申请日：2005-11-04

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  William Tonti

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  William Tonti

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114

    摘要： A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.

    摘要翻译： 一种结构及其形成方法。 该结构包括（a）包括设置在第一和第二S / D区之间的沟道区的半导体层; （b）沟道区上的栅介质区; （c）栅极电介质区域上的栅极区域，并且通过栅极电介质区域与沟道区域电绝缘; （d）栅极区域上的保护伞区域，其中保护伞区域包括第一介电材料，并且其中栅极区域完全处于保护伞区域的阴影中; 和（e）直接在第二S / D区域上方并电连接到第二S / D区域的填充接触孔（i）和（ii）与保护伞区域的边缘对准，其中接触孔通过一个 层间介电层（ILD）层，其包括不同于第一介电材料的第二电介质材料。

    Shrinking Contact Apertures Through LPD Oxide
    47.
    发明申请
    Shrinking Contact Apertures Through LPD Oxide 失效
    通过LPD氧化物收缩接触孔

    公开(公告)号：US20070099416A1

    公开(公告)日：2007-05-03

    申请号：US11163786

    申请日：2005-10-31

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Larry Nesbit

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

    摘要： Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.

    摘要翻译： 通过电介质的亚光刻接触孔形成在电介质，硬掩模和含氧化物种子层的堆叠中。 通过种子层的初始孔径通过液相沉积接收氧化物沉积，该相沉积选择性地粘附到种子层中的孔的暴露的垂直壁。 通过所添加的材料的厚度减小尺寸的亚光刻孔径在硬掩模中限定了减小的孔径。 缩小的硬掩模然后限定通过电介质的亚光刻孔。

    METHOD OF DOPING A GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR
    50.
    发明申请
    METHOD OF DOPING A GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR 失效
    电场效应晶体管的栅极电极的方法

    公开(公告)号：US20060228835A1

    公开(公告)日：2006-10-12

    申请号：US10907569

    申请日：2005-04-06

    申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

    发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L29/4983 ,  H01L29/4908 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78621 ,  Y10S977/742 ,  Y10S977/847

    摘要： A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface ; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.

    摘要翻译： 一种制造结构并制造相关半导体晶体管和新型半导体晶体管结构的方法。 制造该结构的方法包括：提供具有顶表面的基底; 在所述基板的顶表面上形成岛，所述岛的顶表面平行于所述基底的顶表面，所述岛的侧壁在所述岛的顶表面和所述基底的顶表面之间延伸; 在岛的侧壁上形成多个碳纳米管; 并且进行离子注入，所述离子注入在所述岛状体和所述碳纳米管所掩盖的基板的区域中贯穿所述岛并阻止其侵入所述基板。