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    Layer assignment and routing based on resistance or capacitance characteristic
    41.
    发明授权
    Layer assignment and routing based on resistance or capacitance characteristic 有权

    公开(公告)号：US11080457B1

    公开(公告)日：2021-08-03

    申请号：US16823093

    申请日：2020-03-18

    Applicant: Cadence Design Systems, Inc.

    Inventor： Derong Liu ,  Yi-Xiao Ding ,  Mehmet Can Yildiz ,  Zhuo Li

    IPC: G06F30/394 ,  G06F30/392 ,  G06F30/31 ,  G06F30/327 ,  G06F119/12

    Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some embodiments to route the networks on the layers within a certain range that has very close resistance/capacitance (RC) characteristics, and can permit routing each network on layers having the smallest RC characteristic difference.

    Clock gate placement with data path awareness
    43.
    发明授权
    Clock gate placement with data path awareness 有权

    公开(公告)号：US10885250B1

    公开(公告)日：2021-01-05

    申请号：US16735666

    申请日：2020-01-06

    Applicant: Cadence Design Systems, Inc.

    Inventor： David White ,  Andrew Mark Chapman ,  Thomas Andrew Newton ,  Zhuo Li

    IPC: G06F30/3312 ,  G06F30/392 ,  G06F30/396 ,  G06F119/04 ,  G06F117/04

    Abstract: Electronic design automation systems, methods, and media are presented for clock gate placement with data path awareness. One embodiment involves accessing a circuit design with a clock tree, clock gates, and an initial movement area. A set of positions for a set of data path connection points associated with the data routing lines are identified, along with an expansion direction from the initial placement position toward the set of positions for the set of data path connection points, and the initial movement is expanded to consider additional placement options for the clock gate based on the data path connection points.

    Power aware resizing of clock tree instances
    44.
    发明授权
    Power aware resizing of clock tree instances 有权

    公开(公告)号：US10796066B1

    公开(公告)日：2020-10-06

    申请号：US16228418

    申请日：2018-12-20

    Applicant: Cadence Design Systems, Inc.

    Inventor： Amin Farshidi ,  Zhuo Li

    IPC: G06F30/398 ,  G06F30/3312 ,  G06F119/06 ,  G06F119/12

    Abstract: Aspects of the present disclosure address systems and methods for shortening clock-tree wirelength based on target offsets in connected routes. A clock tree comprising routes that interconnect a plurality of clock-tree instances is accessed from memory. A clock-tree instance is selected for evaluation. A baseline power consumption measurement corresponding to a sub-tree of the clock-tree instance with the clock-tree instance at a first size is determined. An alternative power consumption measurement corresponding to the sub-tree of the clock-tree instance with the clock-tree instance at a second size is determined. Based on determining that the baseline power consumption measurement is less than the alternative power consumption measurement, the clock-tree instance is resized according to the second size.

    Systems and methods for assigning clock taps based on timing
    47.
    发明授权
    Systems and methods for assigning clock taps based on timing 有权

    公开(公告)号：US10289775B1

    公开(公告)日：2019-05-14

    申请号：US15694309

    申请日：2017-09-01

    Applicant: Cadence Design Systems, Inc.

    Inventor： Brian Wilson ,  Charles Jay Alpert ,  Zhuo Li

    IPC: G06F17/50

    Abstract: Various embodiments described herein assign, within a circuit design, a clock tap to a clock device (e.g., flip-flop) to improve timing of a path between the clock tap and the clock device. In particular, some embodiments identify which clock devices should be assigned to a clock tap so as to improve final timing as seen under an on-chip variation timing analysis, such an AOCV/CPPR (advanced on-chip variation/common clock path pessimism removal) timing analysis. Some such embodiments may achieve this by identifying, after post-route-optimization, critical clock-tap-to-clock-device assignments based on timing analysis results (e.g., from AOCV/CPPR timing analysis) and feeding back those critical clock-tap-to-clock-device assignments to a process performing new clock tap assignments.

    Pruning redundant buffering solutions using fast timing models
    48.
    发明授权
    Pruning redundant buffering solutions using fast timing models 有权

    公开(公告)号：US11675956B2

    公开(公告)日：2023-06-13

    申请号：US17219748

    申请日：2021-03-31

    Applicant: Cadence Design Systems, Inc.

    Inventor： Jhih-Rong Gao ,  Yi-Xiao Ding ,  Zhuo Li

    IPC: G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  G06F111/04 ,  G06F117/10 ,  G06F119/12

    CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2111/04 ,  G06F2117/10 ,  G06F2119/12

    Abstract: A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

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