公开(公告)号：US07521741B2

公开(公告)日：2009-04-21

申请号：US11593424

申请日：2006-11-06

申请人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

发明人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/0653 ,  H01L29/0692

摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

摘要翻译： 高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。

公开(公告)号：US07521342B2

公开(公告)日：2009-04-21

申请号：US11896883

申请日：2007-09-06

申请人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

IPC分类号： H01L21/04

CPC分类号： H01L29/105 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7833 ,  H01L29/7836

摘要： A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.

摘要翻译： 具有高电压维持能力的半导体结构。 具有高电压维持能力的半导体结构包括第一导电类型的第一阱区域。 与第一导电类型相反的第二导电类型的一对第二阱区分别设置为与第一阱区相邻，并且第一导电类型的抗穿通区域设置在至少第一阱的下部 区域以增加其中的掺杂浓度。 由于抗穿透区域的离子补充，可以进一步降低半导体结构的尺寸而不影响HV维持能力，并且可以防止诸如穿透效果等不期望的影响。

公开(公告)号：US20080191291A1

公开(公告)日：2008-08-14

申请号：US12100888

申请日：2008-04-10

申请人： Chen-Bau Wu ,  Chien-Shao Tang ,  Robin Hsieh ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Chien-Shao Tang ,  Robin Hsieh ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L29/78

CPC分类号： H01L27/092 ,  H01L21/823814 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0852 ,  H01L29/1083 ,  H01L29/7816 ,  H01L29/7835

摘要： A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.

摘要翻译： 提供了适用于高压应用的晶体管。 晶体管形成在具有第一导电类型的深阱的衬底上。 形成第一导电类型的第一阱和第二导电类型的第二阱，使得它们不彼此紧邻。 第一导电类型和第二导电类型的阱可以同时形成用于低电压装置的各个孔。 以这种方式，高压器件可以与具有较少工艺步骤的低电压器件形成在相同的晶片上，从而降低成本和处理时间。 可以在与第二阱相对的一侧上邻近第一阱形成掺杂隔离阱以提供进一步的器件隔离。

公开(公告)号：US20080085579A1

公开(公告)日：2008-04-10

申请号：US11896883

申请日：2007-09-06

申请人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

IPC分类号： H01L21/8238

CPC分类号： H01L29/105 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7833 ,  H01L29/7836

摘要： A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.

摘要翻译： 具有高电压维持能力的半导体结构。 具有高电压维持能力的半导体结构包括第一导电类型的第一阱区域。 与第一导电类型相反的第二导电类型的一对第二阱区分别设置为与第一阱区相邻，并且第一导电类型的抗穿通区域设置在至少第一阱的下部 区域以增加其中的掺杂浓度。 由于抗穿透区域的离子补充，可以进一步降低半导体结构的尺寸而不影响HV维持能力，并且可以防止诸如穿透效果等不期望的影响。

公开(公告)号：US20080001189A1

公开(公告)日：2008-01-03

申请号：US11593424

申请日：2006-11-06

申请人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

发明人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/0653 ,  H01L29/0692

摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

摘要翻译： 高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。

公开(公告)号：US07279767B2

公开(公告)日：2007-10-09

申请号：US11048914

申请日：2005-02-03

申请人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

IPC分类号： H01L23/58

CPC分类号： H01L29/105 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7833 ,  H01L29/7836

摘要： A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.

摘要翻译： 具有高电压维持能力的半导体结构。 具有高电压维持能力的半导体结构包括第一导电类型的第一阱区域。 与第一导电类型相反的第二导电类型的一对第二阱区分别设置为与第一阱区相邻，并且第一导电类型的抗穿通区域设置在至少第一阱的下部 区域以增加其中的掺杂浓度。 由于抗穿透区域的离子补充，可以进一步降低半导体结构的尺寸而不影响HV维持能力，并且可以防止诸如穿透效果等不期望的影响。

公开(公告)号：US20060286735A1

公开(公告)日：2006-12-21

申请号：US11505957

申请日：2006-08-17

申请人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

发明人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

IPC分类号： H01L21/8234

CPC分类号： H01L29/0852 ,  H01L21/74 ,  H01L21/7621 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

摘要翻译： 提供集成电路的晶体管。 在第一有源区的阱层中形成第一掺杂阱区。 第一掺杂阱区的至少一部分与晶体管的栅电极相邻。 在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。 第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。 至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。 第二隔离部分的至少一部分比第一隔离部分低。 漏极掺杂区形成在第一掺杂阱区的凹槽中。 第二隔离部分位于栅电极和漏极掺杂区之间。

公开(公告)号：US20060170060A1

公开(公告)日：2006-08-03

申请号：US11048914

申请日：2005-02-03

申请人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Fang-Cheng Lui ,  Shun-Liang Hsu

IPC分类号： H01L29/76

CPC分类号： H01L29/105 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7833 ,  H01L29/7836

摘要： A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.

公开(公告)号：US20050285218A1

公开(公告)日：2005-12-29

申请号：US10877450

申请日：2004-06-25

申请人： Kuo-Ming Wu ,  Chen-Bau Wu ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Kuo-Ming Wu ,  Chen-Bau Wu ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L29/00 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/7835

摘要： A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the surface of the substrate, thereby minimizing damages to the gate region.

摘要翻译： 公开了具有逆行井的高压装置。 该器件包括衬底，形成在衬底上的栅极区域和位于栅极区域旁边的衬底中的逆行阱，其中逆行阱降低衬底表面上的掺杂剂浓度，从而最小化对栅极区域的损害 。

公开(公告)号：US5641710A

公开(公告)日：1997-06-24

申请号：US661243

申请日：1996-06-10

申请人： Jyh-Haur Wang ,  Shun-Liang Hsu

发明人： Jyh-Haur Wang ,  Shun-Liang Hsu

IPC分类号： H01L21/768 ,  H01L23/485 ,  H01L21/28

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002

摘要： A process has been developed in which an aluminum based, interconnect structure overlies a tungsten plug structure, in a small diameter contact hole. The tungsten plug is formed via RIE removal of unwanted tungsten, from areas other then the contact hole using a halogen containing etchant, and using a RIE overetch cycle that created an unwanted crevice in the center of the tungsten plug. A post RIE anneal, in a nitrogen ambient removes moisture from surrounding dielectric layers and also forms a protective, nitrogen containing tungsten layer, filling the crevice in the tungsten plug. The filling of the crevice allows a planar overlying aluminum based, interconnect structure to be obtained.

摘要翻译： 已经开发了一种在小直径接触孔中铝基互连结构覆盖钨插塞结构的方法。 通过使用含卤素的蚀刻剂从接触孔以外的区域除去不想要的钨，并且使用在钨插塞的中心产生不想要的缝隙的RIE过蚀刻循环，从而形成钨插塞。 在氮环境中的后RIE退火从周围的介电层去除水分，并且还形成保护性的含氮钨层，填充钨塞的缝隙。 缝隙的填充允许获得平面覆盖的铝基互连结构。