公开(公告)号：US06829040B1

公开(公告)日：2004-12-07

申请号：US10703643

申请日：2003-11-07

申请人： Jongwook Kye ,  Ivan Lalovic ,  Christopher F. Lyons ,  Ramkumar Subramanian

发明人： Jongwook Kye ,  Ivan Lalovic ,  Christopher F. Lyons ,  Ramkumar Subramanian

IPC分类号： G03B2742

CPC分类号： G03F7/70575 ,  G03F7/703 ,  G03F7/70333

摘要： A projection lithography system exposes a photo sensitive material on a surface of a semiconductor substrate that includes surface height variations between a high level and a low level. The system comprises an illumination source projecting illumination within a narrow wavelength band centered about a nominal wavelength on an optic path towards the substrate during an exposure period. A wavelength modulation system within the optic path comprises means for chromatically separating the narrow wavelength band into at least two sub-bands, the first sub-band being smaller than the narrow wavelength band and centered about a first sub-band wavelength and the second sub-band being smaller than the narrow wavelength band and centered about a second sub-band wavelength and means for passing each of the first sub-band and the second sub-band during distinct time periods within the exposure period.

摘要翻译： 投影光刻系统在半导体衬底的表面上曝光感光材料，其包括高电平和低电平之间的表面高度变化。 该系统包括照射源，其在曝光期间内以在光路上朝着衬底的标称波长为中心的窄波长带内投射照明。 光路内的波长调制系统包括用于将窄波段色带分离成至少两个子带的装置，第一子带小于窄波段并以第一子带波长为中心，第二子带 带窄于窄波长带并以第二子带波长为中心，以及用于在曝光周期内的不同时间段内通过第一子带和第二子带中的每一个的装置。

公开(公告)号：US06787458B1

公开(公告)日：2004-09-07

申请号：US10614397

申请日：2003-07-07

申请人： Nicholas H. Tripsas ,  Matthew S. Buynoski ,  Suzette K. Pangrle ,  Uzodinma Okoroanyanwu ,  Angela T. Hui ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Ashok M. Khathuria ,  Mark S. Chang ,  Patrick K. Cheung ,  Jane V. Oglesby

发明人： Nicholas H. Tripsas ,  Matthew S. Buynoski ,  Suzette K. Pangrle ,  Uzodinma Okoroanyanwu ,  Angela T. Hui ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Ashok M. Khathuria ,  Mark S. Chang ,  Patrick K. Cheung ,  Jane V. Oglesby

IPC分类号： H01L2144

CPC分类号： H01L27/285 ,  H01L2924/0002 ,  H01L2924/00

摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.

摘要翻译： 本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。 该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔 露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

公开(公告)号：US06773998B1

公开(公告)日：2004-08-10

申请号：US10445129

申请日：2003-05-20

申请人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/3146 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.

摘要翻译： 集成电路的方法包括使用无定形碳ARC掩模。 一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。 蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。 然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

公开(公告)号：US06654660B1

公开(公告)日：2003-11-25

申请号：US10287292

申请日：2002-11-04

申请人： Bhanwar Singh ,  Christopher F. Lyons ,  Bharath Rangarajan ,  Khoi A. Phan ,  Ramkumar Subramanian

发明人： Bhanwar Singh ,  Christopher F. Lyons ,  Bharath Rangarajan ,  Khoi A. Phan ,  Ramkumar Subramanian

IPC分类号： G06F1900

CPC分类号： G03F7/70425 ,  G03F7/70875

摘要： One aspect of the present invention relates to a system and method for controlling thermal expansion on an EUV mask during EUV photolithography. The system includes an EUV photolithography system for irradiating one or more layers of a wafer through one or more gratings of a patterned EUV mask, whereby heat accumulates on at least a portion of the patterned EUV mask during the irradiation of the one or more layers of the wafer; an EUV mask inspection system for monitoring the one or more gratings on the mask to detect expansion therein, the inspection system producing data relating to the mask; and a temperature control system operatively coupled to the inspection system for making adjustments to the EUV photolithography system in order to compensate for the detected expansion on the mask. The method involves employing feedback and feed forward control to optimize the current and future EUV photolithography processes.

摘要翻译： 本发明的一个方面涉及一种用于在EUV光刻期间控制EUV掩模上的热膨胀的系统和方法。 该系统包括用于通过图案化的EUV掩模的一个或多个光栅照射晶片的一个或多个层的EUV光刻系统，由此在图案化的EUV掩模的照射期间在图案化的EUV掩模的至少一部分上积聚热量 晶圆; 用于监视所述掩模上的所述一个或多个光栅以检测其中的扩展的EUV掩模检查系统，所述检查系统产生与所述掩模有关的数据; 以及温度控制系统，其可操作地耦合到所述检查系统，以对EUV光刻系统进行调整，以便补偿所述掩模上检测到的膨胀。 该方法涉及采用反馈和前馈控制来优化当前和未来的EUV光刻工艺。

公开(公告)号：US06635409B1

公开(公告)日：2003-10-21

申请号：US09902568

申请日：2001-07-12

申请人： Christopher F. Lyons ,  Scott A. Bell ,  Todd Lukanc ,  Marina V. Plat

发明人： Christopher F. Lyons ,  Scott A. Bell ,  Todd Lukanc ,  Marina V. Plat

IPC分类号： G03F700

CPC分类号： G03F7/40 ,  G03F7/2024

摘要： There is provided a method for forming a photoresist layer for photolithographic applications which has increased structural strength. The photoresist layer is exposed through a mask and developed. The photoresist layer is then treated to change its material properties before the photoresist layer is dried. Also provided are a semiconductor fabrication method employing a treated photoresist and a composition for a treatable photoresist.

摘要翻译： 提供了一种形成光刻应用的光致抗蚀剂层的方法，其具有增加的结构强度。 光致抗蚀剂层通过掩模曝光并显影。 然后在光致抗蚀剂层干燥之前，处理光致抗蚀剂层以改变其材料性质。 还提供了使用经处理的光致抗蚀剂和用于可处理光致抗蚀剂的组合物的半导体制造方法。

公开(公告)号：US06558965B1

公开(公告)日：2003-05-06

申请号：US09901702

申请日：2001-07-11

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Christopher F. Lyons ,  Marina V. Plat

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Christopher F. Lyons ,  Marina V. Plat

IPC分类号： H01L2166

CPC分类号： G03F7/091 ,  G01B11/0616 ,  H01L21/0276

摘要： A method of forming a semiconductor device is described. A bottom anti-reflective coating (BARC) is formed in a plurality of holes and on a first surface of a layer of a semiconductor device. A scatterometry measurement on at least a portion of the BARC is performed to produce measurement diffraction data. A thickness of the BARC in the plurality of holes is predicted by comparing the first diffraction data to a model of diffraction data to provide a predicted thickness, tp, and it is determined if the predicted thickness, tp, is within a target thickness range, &Dgr;td. The forming of the BARC is controlled in response to the prediction of the BARC thickness. A corresponding thickness control device for controlling the BARC thickness is also disclosed.

摘要翻译： 描述形成半导体器件的方法。 底部抗反射涂层（BARC）形成在多个孔中以及在半导体器件的层的第一表面上。 执行至少一部分BARC的散射测量以产生测量衍射数据。 通过将第一衍射数据与衍射数据的模型进行比较以提供预测厚度tp来预测多个孔中的BARC的厚度，并且确定预测厚度tp是否在目标厚度范围内， DELTAtd。 响应于BARC厚度的预测，控制BARC的形成。 还公开了用于控制BARC厚度的相应的厚度控制装置。

公开(公告)号：US06541360B1

公开(公告)日：2003-04-01

申请号：US09845649

申请日：2001-04-30

申请人： Marina V. Plat ,  Scott A. Bell ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh

发明人： Marina V. Plat ,  Scott A. Bell ,  Christopher F. Lyons ,  Ramkumar Subramanian ,  Bhanwar Singh

IPC分类号： H01L213205

CPC分类号： H01L21/0338 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/952

摘要： A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etching the organic underlayer to form a pattern, and removing portions of the polysilicon layer using the pattern formed from the removed portions of organic underlayer. Thus, the use of thin imaging layer, that has high etch selectivity to the organic underlayer, allows the use of trim etch techniques without a risk of resist erosion or the aspect ratio pattern collapse. That, in turn, allows for the formation of the gate pattern with widths less than the widths of the pattern of the imaging layer.

摘要翻译： 用于形成集成电路栅极结构的双层修剪蚀刻工艺可以包括在多晶硅层上沉积有机底层，在有机底层上沉积成像层，图案化成像层，选择性地修整蚀刻有机底层以形成图案， 以及使用由有机底层的去除部分形成的图案去除多晶硅层的部分。 因此，对有机底层具有高蚀刻选择性的薄成像层的使用允许使用微调蚀刻技术，而不会有抗蚀剂侵蚀或长宽比图案崩溃的风险。 这又反过来允许形成具有小于成像层的图案的宽度的宽度的栅极图案。

公开(公告)号：US06448164B1

公开(公告)日：2002-09-10

申请号：US09716216

申请日：2000-11-21

申请人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Marina V. Plat ,  Todd P. Lukanc

发明人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Marina V. Plat ,  Todd P. Lukanc

IPC分类号： H01L213205

CPC分类号： H01L21/0274 ,  H01L21/28123

摘要： A method of forming either a gate pattern or a line pattern in a resist by using a dark field mask and a combination of a negative photoresist and a positive photoresist. The dark field mask is used to create a hole within the positive photoresist, by exposing only a portion of the positive photoresist to light, and then by subjecting the positive photoresist to a developer. The negative photoresist is formed within the hole of the positive photoresist, and etched or polished so that it is only disposed within the hole. The negative photoresist and the positive photoresist are subjected to a flood light exposure, and then to a developer. This causes the positive photoresist to dissolve, leaving the negative photoresist, thereby providing a very-small-dimension resist pattern that can be used to form either a gate or a line for a semiconductor device.

摘要翻译： 通过使用暗场掩模和负光致抗蚀剂和正性光致抗蚀剂的组合在抗蚀剂中形成栅极图案或线图案的方法。 暗场掩模用于在正性光致抗蚀剂中产生孔，通过仅将一部分正性光致抗蚀剂暴露于光，然后通过使正性光致抗蚀剂经受显影剂。 负光致抗蚀剂形成在正性光致抗蚀剂的孔内，并被蚀刻或抛光，使得其仅设置在孔内。 对负性光致抗蚀剂和正性光致抗蚀剂进行泛光曝光，然后进行显影。 这导致正性光致抗蚀剂溶解，留下负性光致抗蚀剂，从而提供可用于形成半导体器件的栅极或线的非常小的抗蚀剂图案。

公开(公告)号：US06383952B1

公开(公告)日：2002-05-07

申请号：US09794632

申请日：2001-02-28

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Marina V. Plat ,  Christopher F. Lyons ,  Scott A. Bell

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Marina V. Plat ,  Christopher F. Lyons ,  Scott A. Bell

IPC分类号： H01L2131

CPC分类号： H01L21/0271 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338

摘要： A method of doubling the frequency of small pattern formation. The method includes forming a photoresist layer, and then patterning it. A RELACS polymer is spread over the patterned photoresist layer. Portions of the RELACS polymer on top portions of each patterned photoresist region are removed, by either etching or by polishing them off. Portions between each patterned photoresist region are also removed in this step. The patterned photoresist regions are removed, preferably by a flood exposure and then application of a developer to the exposed photoresist regions. The remaining RELACS polymer regions, which were disposed against respective sidewalls of the patterned photoresist regions, prior to their removal, are then used for forming small pattern regions to be used in a semiconductor device to be formed on the substrate. These small pattern regions can be used to form separate poly-gates.

摘要翻译： 一种将图案形成加倍的方法。 该方法包括形成光致抗蚀剂层，然后对其进行图案化。 RELACS聚合物分散在图案化的光致抗蚀剂层上。 通过蚀刻或通过抛光，去除每个图案化的光致抗蚀剂区域的顶部上的部分RELACS聚合物。 在该步骤中也去除了每个图案化的光致抗蚀剂区域之间的部分。 去除图案化的光致抗蚀剂区域，优选通过暴露曝光，然后将显影剂施加到曝光的光致抗蚀剂区域。 然后将其去除之前设置在图案化光致抗蚀剂区域的相应侧壁上的剩余RELACS聚合物区域用于形成待用于形成在衬底上的半导体器件中的小图案区域。 这些小图案区域可用于形成单独的多门。

公开(公告)号：US06326319B1

公开(公告)日：2001-12-04

申请号：US09609746

申请日：2000-07-03

申请人： Christopher L. Pike ,  Khanh B. Nguyen ,  Christopher F. Lyons

发明人： Christopher L. Pike ,  Khanh B. Nguyen ,  Christopher F. Lyons

IPC分类号： H01F1002

CPC分类号： H01L21/02312 ,  G03F7/16 ,  G03F7/162 ,  H01L21/02109 ,  H01L21/02307 ,  H01L21/312 ,  H01L21/3125

摘要： There is provided a method for applying a lower viscosity coating liquid onto a semiconductor wafer substrate so as to prevent adhesion loss and to maintain low defect level characteristics. This is achieved by priming the substrate with a bonding agent at a temperature in the range of 18° C. to 50° C. for a short amount of time. This is performed prior to the application of a liquid solvent. As a result, there is overcome the problems of poor adhesion to the substrates and high defect levels in the coated UTR films.

摘要翻译： 提供了一种将低粘度涂布液施加到半导体晶片衬底上以防止粘附损失并保持低缺陷水平特性的方法。 这是通过用粘合剂在18℃至50℃的温度范围内引发基底短时间来实现的。 这是在施加液体溶剂之前进行的。 结果，克服了在涂覆的UTR膜中对基材的粘附性差和高缺陷水平的问题。