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公开(公告)号：US06326319B1
公开(公告)日：2001-12-04
申请号：US09609746
申请日：2000-07-03
IPC分类号： H01F1002
CPC分类号： H01L21/02312 , G03F7/16 , G03F7/162 , H01L21/02109 , H01L21/02307 , H01L21/312 , H01L21/3125
摘要： There is provided a method for applying a lower viscosity coating liquid onto a semiconductor wafer substrate so as to prevent adhesion loss and to maintain low defect level characteristics. This is achieved by priming the substrate with a bonding agent at a temperature in the range of 18° C. to 50° C. for a short amount of time. This is performed prior to the application of a liquid solvent. As a result, there is overcome the problems of poor adhesion to the substrates and high defect levels in the coated UTR films.
摘要翻译： 提供了一种将低粘度涂布液施加到半导体晶片衬底上以防止粘附损失并保持低缺陷水平特性的方法。 这是通过用粘合剂在18℃至50℃的温度范围内引发基底短时间来实现的。 这是在施加液体溶剂之前进行的。 结果，克服了在涂覆的UTR膜中对基材的粘附性差和高缺陷水平的问题。
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公开(公告)号：US06309926B1
公开(公告)日：2001-10-30
申请号：US09205211
申请日：1998-12-04
申请人： Scott A. Bell , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Chih Yuh Yang
发明人： Scott A. Bell , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Chih Yuh Yang
IPC分类号： H01L218242
CPC分类号： H01L27/11521 , H01L21/0274 , H01L21/31116 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L27/115
摘要： A method of forming a gate structure is provided. In the method, a nitride layer is formed on a gate material layer. An ultra-thin photoresist layer is formed on the nitride layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for the gate. The ultra-thin photoresist layer is used as a mask during a first etch step to transfer the gate pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer. The nitride layer is used as a hard mask during a second etch step to form the gate by transferring the gate pattern to the gate material layer via the second etch step.
摘要翻译： 提供一种形成栅极结构的方法。 在该方法中，在栅极材料层上形成氮化物层。 在氮化物层上形成超薄的光致抗蚀剂层。 用短波长辐射对超薄光致抗蚀剂层进行构图，以限定栅极的图案。 在第一蚀刻步骤期间，将超薄光致抗蚀剂层用作掩模，以将栅极图案转移到氮化物层。 第一蚀刻步骤包括对超薄光致抗蚀剂层上的氮化物层有选择性的蚀刻化学品。 在第二蚀刻步骤期间，氮化物层用作硬掩模，以通过经由第二蚀刻步骤将栅极图案转移到栅极材料层来形成栅极。
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3.发明授权
公开(公告)号：US06165695A
公开(公告)日：2000-12-26
申请号：US203150
申请日：1998-12-01
申请人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
发明人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
IPC分类号： H01L21/027 , H01L21/033 , H01L21/311 , H01L21/768 , G03C5/00
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/76816 , Y10S430/168
摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amorphous silicon layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the amorphous silicon layer. The first etch step includes an etch chemistry that is selective to the amorphous silicon layer over the ultra-thin photoresist layer and the dielectric layer. The amorphous silicon layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.
摘要翻译： 提供一种形成通孔结构的方法。 在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在该电介质层上形成非晶硅层。 在非晶硅层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行构图，以限定通孔的图案。 在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转印到非晶硅层。 第一蚀刻步骤包括对超薄光致抗蚀剂层和介电层上的非晶硅层有选择性的蚀刻化学品。 在第二蚀刻步骤期间，非晶硅层用作硬掩模，以通过蚀刻介电层的部分形成对应于通孔图案的接触孔。
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公开(公告)号：US6156658A
公开(公告)日：2000-12-05
申请号：US203774
申请日：1998-12-02
申请人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
发明人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
IPC分类号： H01L21/027 , H01L21/3213 , H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/0274 , H01L21/32136
摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon layer over the oxide layer; depositing an ultra-thin photoresist over the silicon layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon layer; etching the exposed portion of the silicon layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.
摘要翻译： 在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：提供包括金属层的半导体衬底，金属层上的氧化物层和氧化物层上的硅层; 在硅层上沉积超薄光致抗蚀剂，超薄光致抗蚀剂的厚度小于约2,000安培; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 开发暴露一部分硅层的超薄光刻胶; 蚀刻暴露出氧化物层的一部分的硅层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。
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公开(公告)号：US06057206A
公开(公告)日：2000-05-02
申请号：US410526
申请日：1999-10-01
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/54493 , H01L2924/0002
摘要： A method of forming an alignment mark protection structure is disclosed and includes forming an alignment mark protection layer over a substrate which has an alignment mark associated therewith. The method also includes forming a negative photoresist layer over the alignment mark protection layer and removing a portion of the negative photoresist layer which does not overlie the alignment mark. The removal exposes a portion of the alignment mark protection layer which does not overlie the alignment mark and the exposed portion of the alignment mark protection layer is then removed. Preferably, the removal of a portion of the negative photoresist includes selectively exposing a peripheral portion thereof using an edge-bead removal tool, thereby allowing for the formation of an alignment mark protection structure without an extra masking step.
摘要翻译： 公开了一种形成对准标记保护结构的方法，并且包括在具有与其相关联的对准标记的衬底上形成对准标记保护层。 该方法还包括在对准标记保护层上形成负光致抗蚀剂层，并且去除不覆盖对准标记的负光致抗蚀剂层的一部分。 去除暴露出不覆盖对准标记的对准标记保护层的一部分，然后去除对准标记保护层的暴露部分。 优选地，去除负光致抗蚀剂的一部分包括使用边缘珠去除工具选择性地暴露其周边部分，从而允许形成对准标记保护结构而没有额外的掩模步骤。
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6.发明授权公开(公告)号：US06440640B1
公开(公告)日：2002-08-27
申请号：US09703092
申请日：2000-10-31
申请人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
发明人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
IPC分类号： G03C500
CPC分类号： H01L21/76816 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/32139
摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.
摘要翻译： 提供一种形成通孔结构的方法。 在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在介电层上形成过渡金属层。 在过渡金属层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行构图，以形成通孔图案。 在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转印到过渡金属层。 第一蚀刻步骤包括对超薄光致抗蚀剂层和电介质层上的过渡金属层有选择性的蚀刻化学品。 在第二蚀刻步骤期间，过渡金属层用作硬掩模，以通过蚀刻介电层的部分形成与通孔图案相对应的接触孔。
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7.发明授权Tuning substrate/resist contrast to maximize defect inspection sensitivity for ultra-thin resist in DUV lithography 失效调整衬底/抗蚀剂对比度，以最大化DUV光刻中超薄抗蚀剂的缺陷检测灵敏度公开(公告)号：US06316277B1
公开(公告)日：2001-11-13
申请号：US09580612
申请日：2000-05-30
IPC分类号： H01L2166
CPC分类号： H01L22/24
摘要： There is provided a method for enhancing the contrast between oxide film and ultra-thin resists in deep-ultraviolet lithography for use with a wafer defect inspection system in order to maximize defect inspection sensitivity. This is achieved by varying the thickness of the oxide film for a given ultra-thin resist thickness so as to produce a high contrast. As a result, defect inspection of the ultra-thin resist pattern is easily obtained. In a second embodiment, the ultra-thin resist thickness is varied for a given oxide film thickness. In a third embodiment, both the oxide film and the ultra-thin resist thicknesses are varied simultaneously so as to obtain an optimum contrast.
摘要翻译： 提供了一种用于在深紫外线光刻中增强氧化膜和超薄抗蚀剂之间的对比度以与晶片缺陷检查系统一起使用以便最大化缺陷检查灵敏度的方法。 这是通过改变给定的超薄抗蚀剂厚度的氧化膜的厚度来实现的，以产生高对比度。 结果，容易获得超薄抗蚀剂图案的缺陷检查。 在第二实施例中，对于给定的氧化膜厚度，超薄抗蚀剂厚度是变化的。 在第三实施例中，氧化膜和超薄抗蚀剂厚度同时变化，以获得最佳对比度。
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8.发明授权公开(公告)号：US06200907B1
公开(公告)日：2001-03-13
申请号：US09204216
申请日：1998-12-02
申请人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
发明人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
IPC分类号： H01L21302
CPC分类号： H01L21/32139 , H01L21/0275 , H01L21/0332 , H01L21/31111 , H01L21/31116 , H01L21/76838
摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a barrier metal layer over the oxide layer; depositing an ultra-thin photoresist over the barrier metal layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the barrier metal layer; etching the exposed portion of the barrier metal layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.
摘要翻译： 在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：提供包括金属层的半导体衬底，金属层上的氧化物层和氧化物层上的阻挡金属层; 在阻挡金属层上沉积超薄光致抗蚀剂，超薄光致抗蚀剂具有小于约的厚度; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 显影暴露一部分阻挡金属层的超薄光刻胶; 蚀刻暴露部分氧化物层的阻挡金属层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。
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公开(公告)号：US06184128B2
公开(公告)日：2001-02-06
申请号：US09497222
申请日：2000-01-31
申请人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
发明人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
IPC分类号： H01L214763
CPC分类号： H01L21/7681 , H01L21/31144
摘要： In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first photoresist thereby exposing a portion of the first low k material layer; removing the first photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second photoresist thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions of the first and second low k material layers; and removing the second photoresist, wherein and at least one of the first photoresist and the second photoresist have a thickness of about 1,500 Å or less.
摘要翻译： 在一个实施例中，本发明涉及一种双镶嵌方法，包括以下步骤：提供具有第一低k材料层的基底; 在所述第一低k材料层上形成第一硬掩模层; 使用第一光致抗蚀剂构图在第一硬掩模层中具有第一宽度的第一开口，从而暴露第一低k材料层的一部分; 去除第一光致抗蚀剂; 在图案化的第一硬掩模层和第一低k材料层的暴露部分上沉积第二低k材料层; 在所述第二低k材料层上形成第二硬掩模层; 使用第二光致抗蚀剂构图在第二硬掩模层中形成具有大于第一宽度的宽度的第二开口，从而暴露第二低k材料层的一部分; 各向异性地蚀刻第一和第二低k材料层的暴露部分; 并且去除所述第二光致抗蚀剂，其中所述第一光致抗蚀剂和所述第二光致抗蚀剂中的至少一个具有大约等于或小于1500埃的厚度。
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10.发明授权Ultra-thin resist shallow trench process using high selectivity nitride etch 有权使用高选择性氮化物蚀刻的超薄抗蚀剂浅沟槽工艺公开(公告)号：US06740566B2
公开(公告)日：2004-05-25
申请号：US09398641
申请日：1999-09-17
申请人： Christopher F. Lyons , Scott A. Bell , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Chih Yuh Yang
发明人： Christopher F. Lyons , Scott A. Bell , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Chih Yuh Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench. In another embodiment, the method further involves depositing an insulating filler material into the shallow trench to provide a shallow trench isolation region.
摘要翻译： 在一个实施例中，本发明涉及一种形成浅沟槽的方法，包括以下步骤：在半导体衬底上提供包括阻挡氧化物层的半导体衬底，以及在阻挡氧化物层上方的氮化物层; 在所述氮化物层上沉积超薄光致抗蚀剂，所述超薄光致抗蚀剂具有约2,000或更小的厚度; 图案化超薄光致抗蚀剂以暴露氮化物层的一部分并且限定用于浅沟槽的图案; 用具有至少约10:1的氮化物：光致抗蚀剂选择性的蚀刻剂蚀刻氮化物层的暴露部分以暴露部分阻挡氧化物层; 蚀刻阻挡氧化物层的暴露部分以暴露半导体衬底的一部分; 并蚀刻半导体衬底的暴露部分以提供浅沟槽。 在另一个实施例中，该方法还包括将绝缘填充材料沉积到浅沟槽中以提供浅沟槽隔离区域。
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