公开(公告)号：US20110163360A1

公开(公告)日：2011-07-07

申请号：US13048976

申请日：2011-03-16

申请人： Da Zhang ,  Ning Liu ,  Mohamed S. Moosa

发明人： Da Zhang ,  Ning Liu ,  Mohamed S. Moosa

IPC分类号： H01L29/772

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.

摘要翻译： 通过提供半导体衬底并在半导体衬底上方提供栅极形成晶体管结构。 栅极通过栅极绝缘层与半导体衬底分离。 在栅极附近提供源极和漏极，以限定栅极下方的晶体管沟道，并通过栅极绝缘层与栅极分离。 通过在晶体管沟道和源极和漏极中的每一个之间的晶体管沟道的相对的外部垂直侧上施加氮或碳来形成阻挡层。 在氮和碳实施方案中的每一个中，垂直沟道障碍阻止源极/漏极掺杂剂物质扩散到晶体管沟道中。 存在用于形成晶体管结构的方法。

公开(公告)号：US07927989B2

公开(公告)日：2011-04-19

申请号：US11829156

申请日：2007-07-27

申请人： Da Zhang ,  Ning Liu ,  Mohamed S. Moosa

发明人： Da Zhang ,  Ning Liu ,  Mohamed S. Moosa

IPC分类号： H01L21/336 ,  H01L21/425

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.

摘要翻译： 通过提供半导体衬底并在半导体衬底上方提供栅极形成晶体管结构。 栅极通过栅极绝缘层与半导体衬底分离。 在栅极附近提供源极和漏极，以限定栅极下方的晶体管沟道，并通过栅极绝缘层与栅极分离。 通过在晶体管沟道和源极和漏极中的每一个之间的晶体管沟道的相对的外部垂直侧上施加氮或碳来形成阻挡层。 在氮和碳实施方案中的每一个中，垂直沟道障碍阻止源极/漏极掺杂剂物质扩散到晶体管沟道中。 存在用于形成晶体管结构的方法。

公开(公告)号：US07858482B2

公开(公告)日：2010-12-28

申请号：US12059286

申请日：2008-03-31

申请人： Da Zhang ,  Christopher C. Hobbs ,  Srikanth B. Samavedam

发明人： Da Zhang ,  Christopher C. Hobbs ,  Srikanth B. Samavedam

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L21/823412 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7847

摘要： A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.

摘要翻译： 应力记忆技术（SMT）膜沉积在半导体器件上。 SMT薄膜通过低热预算退火进行退火，该退火足以产生并将SMT薄膜的应力转移到半导体器件。 然后去除SMT膜。 在去除SMT膜之后，对半导体器件施加足够长的时间并在足够高的温度下进行第二次退火以激活植入用于形成器件源极/漏极的掺杂剂。 这种方法的结果是沿通道边界的通道中存在最小的栅介质生长。

公开(公告)号：US07833852B2

公开(公告)日：2010-11-16

申请号：US11781610

申请日：2007-07-23

申请人： Brian A. Winstead ,  Vishal P. Trivedi ,  Da Zhang

发明人： Brian A. Winstead ,  Vishal P. Trivedi ,  Da Zhang

IPC分类号： H01L21/335

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

摘要： A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括形成半导体层。 该方法还包括形成覆盖半导体层的栅极结构。 该方法还包括形成邻近门结构的高k侧壁间隔物。 所述方法还包括在所述半导体层中形成凹部，所述凹部与所述高k侧壁间隔物对准。 所述方法还包括在所述凹部中形成原位掺杂的外延材料，所述外延材料具有不同于所述半导体层的晶格常数的天然晶格常数，以在所述半导体器件的沟道区域中产生应力。

公开(公告)号：US20090291540A1

公开(公告)日：2009-11-26

申请号：US12125855

申请日：2008-05-22

申请人： Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

发明人： Da Zhang ,  Srikanth B. Samavedam ,  Voon-Yew Thean ,  Xiangdong Chen

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.

摘要翻译： 半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34） 以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积 接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。 也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

公开(公告)号：US07544997B2

公开(公告)日：2009-06-09

申请号：US11676114

申请日：2007-02-16

申请人： Da Zhang ,  Veeraraghavan Dhandapani ,  Darren V. Goedeke ,  Jill C. Hildreth

发明人： Da Zhang ,  Veeraraghavan Dhandapani ,  Darren V. Goedeke ,  Jill C. Hildreth

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.

摘要翻译： 一种形成半导体器件的方法包括在半导体器件的源极区域和漏极区域中形成凹部。 该方法还包括在源极区域的凹部中形成第一半导体材料层和在漏极区域的凹部中形成第二半导体材料层，其中第一半导体材料层和第二半导体材料层中的每一个使用应力源 具有第一元素的原子浓度和第二元素的原子浓度的第一比率的材料，其中第一元素是硅，并且掺杂材料的第一浓度水平。 该方法还包括形成覆盖第一半导体材料层和第二半导体材料层的附加半导体材料层，其具有与第一元件和第二元件的原子浓度不同的比率。

公开(公告)号：US20090091280A1

公开(公告)日：2009-04-09

申请号：US12202574

申请日：2008-09-02

申请人： Da Zhang ,  Hui Li ,  Emmanuel G. Collins

发明人： Da Zhang ,  Hui Li ,  Emmanuel G. Collins

IPC分类号： H02P1/04

CPC分类号： H02P21/0003

摘要： Different circuit-based implementations of stochastic anti-windup PI controllers are provided for a motor drive controller system. The designs can be implemented in a Field Programmable Gate Arrays (FPGA) device. The anti-windup PI controllers are implemented stochastically so as to enhance the computational capability of FPGA.

摘要翻译： 为电机驱动控制器系统提供了不同的基于电路的随机反卷积PI控制器的实现。 这些设计可以在现场可编程门阵列（FPGA）器件中实现。 防结块PI控制器随机实现，以提高FPGA的计算能力。

公开(公告)号：US20090026554A1

公开(公告)日：2009-01-29

申请号：US11781610

申请日：2007-07-23

申请人： Brian A. Winstead ,  Vishal P. Trivedi ,  Da Zhang

发明人： Brian A. Winstead ,  Vishal P. Trivedi ,  Da Zhang

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

摘要： A method for forming a semiconductor device is provided. The method includes forming a semiconductor layer. The method further includes forming a gate structure overlying the semiconductor layer. The method further includes forming a high-k sidewall spacer adjacent to the gate structure. The method further includes forming a recess in the semiconductor layer, the recess aligned to the high-k sidewall spacer. The method further includes forming an in-situ doped epitaxial material in the recess, the epitaxial material having a natural lattice constant different from a lattice constant of the semiconductor layer to create stress in a channel region of the semiconductor device.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括形成半导体层。 该方法还包括形成覆盖半导体层的栅极结构。 该方法还包括形成邻近门结构的高k侧壁间隔物。 所述方法还包括在所述半导体层中形成凹部，所述凹部与所述高k侧壁间隔物对准。 所述方法还包括在所述凹部中形成原位掺杂的外延材料，所述外延材料具有不同于所述半导体层的晶格常数的天然晶格常数，以在所述半导体器件的沟道区域中产生应力。

公开(公告)号：US20080261362A1

公开(公告)日：2008-10-23

申请号：US11737496

申请日：2007-04-19

申请人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

发明人： Da Zhang ,  Xiangzheng Bo ,  Venkat R. Kolagunta

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.

摘要翻译： 一种用于形成半导体器件的方法包括提供衬底并形成p沟道器件和n沟道器件，每个p沟道器件和n沟道器件包括源极，漏极和栅极， p沟道器件具有第一侧壁间隔物，并且所述n沟道器件具有第二侧壁间隔物。 该方法还包括形成衬套并在衬套上形成拉伸应力层，并从覆盖p沟道器件的区域去除拉伸应力层的一部分。 该方法还包括将拉伸应力层的剩余部分的上覆部分的应力特性转移到n沟道器件的通道。 该方法还包括使用拉伸应力层的剩余部分作为硬掩模，形成邻近p沟道器件的栅极的第一凹槽和第二凹槽。

公开(公告)号：US20080197412A1

公开(公告)日：2008-08-21

申请号：US11676114

申请日：2007-02-16

申请人： Da Zhang ,  Veeraraghavan Dhandapani ,  Darren V. Goedeke ,  Jill C. Hildreth

发明人： Da Zhang ,  Veeraraghavan Dhandapani ,  Darren V. Goedeke ,  Jill C. Hildreth

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.

摘要翻译： 一种形成半导体器件的方法包括在半导体器件的源极区域和漏极区域中形成凹部。 该方法还包括在源极区域的凹部中形成第一半导体材料层和在漏极区域的凹部中形成第二半导体材料层，其中第一半导体材料层和第二半导体材料层中的每一个使用应力源 具有第一元素的原子浓度和第二元素的原子浓度的第一比率的材料，其中第一元素是硅，并且掺杂材料的第一浓度水平。 该方法还包括形成覆盖第一半导体材料层和第二半导体材料层的附加半导体材料层，其具有与第一元件和第二元件的原子浓度不同的比率。