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公开(公告)号：US07645651B2
公开(公告)日：2010-01-12
申请号：US11951702
申请日：2007-12-06
IPC分类号： H01L21/00 , H01L21/84 , H01L21/337 , H01L21/8238 , H01L21/8236 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66659 , H01L29/7781
摘要： A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device. During a portion of forming the remainder of the MOS device, dopant of the first conductivity type of the first doped region of the active area and dopant of the second conductivity type of the second doped region of the active area diffuses into overlying portions of the strained semiconductor layer to create a correspondingly doped strained semiconductor layer, thereby providing corresponding doping for the biaxially strained channel.
摘要翻译： 一种形成金属氧化物半导体（MOS）器件的方法包括：在非限制性半导体层结构中限定有源区，沉积覆盖有源区的硬掩模和有源区外的区域，使硬掩模图形化以暴露有源区 选择性地生长覆盖暴露的有源区的应变半导体层，以及形成MOS器件的其余部分。 有源区包括第一导电类型的第一掺杂区和第二导电类型的第二掺杂区。 应变半导体层为MOS器件提供双向应变通道。 在形成MOS器件的其余部分的部分期间，有源区的第一掺杂区的第一导电类型的掺杂剂和有源区的第二掺杂区的第二导电类型的掺杂剂扩散到应变的上覆部分 以产生相应掺杂的应变半导体层，从而为双轴应变通道提供相应的掺杂。
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公开(公告)号：US20080293192A1
公开(公告)日：2008-11-27
申请号：US11751724
申请日：2007-05-22
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/26506 , H01L29/665 , H01L29/66628 , H01L29/66772 , H01L29/7843
摘要： A semiconductor device is formed in a semiconductor layer. A gate dielectric is formed over a top surface of the semiconductor layer. A gate stack is over the gate dielectric. A sidewall spacer is formed around the gate stack. Using the sidewall spacer as a mask, an implant is performed to form deep source/drain regions in the semiconductor layer. Silicon carbon regions are formed on the deep source/drain regions and a top surface of the gate stack. The silicon carbon regions are silicided with nickel.
摘要翻译： 在半导体层中形成半导体器件。 在半导体层的顶表面上形成栅极电介质。 栅极堆叠在栅极电介质上方。 在栅堆叠周围形成侧壁间隔物。 使用侧壁间隔件作为掩模，进行注入以在半导体层中形成深的源极/漏极区域。 在深源极/漏极区域和栅极堆叠的顶表面上形成硅碳区域。 硅碳区域用镍硅化。
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公开(公告)号：US07416605B2
公开(公告)日：2008-08-26
申请号：US11620987
申请日：2007-01-08
CPC分类号： H01L29/7848 , H01L29/1054 , H01L29/665 , H01L29/66636 , H01L29/7834
摘要： An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.
摘要翻译： 包含IV族元素组合的外延生长的晶体半导体层的退火。 该层含有碳和锡中的至少一种。 外延生长材料层在峰值温度的10％以内，在1000〜1400摄氏度的温度下退火不超过100毫秒。 退火例如通过激光退火或闪光灯退火来进行。 有限时间退火可以改善晶体管的载流子迁移率。
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公开(公告)号：US07736957B2
公开(公告)日：2010-06-15
申请号：US11756095
申请日：2007-05-31
申请人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
发明人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.
摘要翻译： 一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅电极的侧壁上形成绝缘层; 限定与绝缘层相邻的半导体衬底中的源区和漏区; 在所述半导体衬底的源区和漏区中注入掺杂剂以形成掺杂源极和漏极区; 形成邻近所述绝缘层的侧壁间隔物; 在所述源极和漏极区域中的所述半导体衬底中形成凹部，其中所述凹部直接在所述间隔物的下方延伸距离沟道区域预定的距离; 以及在所述凹部中形成应力源材料。 该方法允许应力源材料形成得更靠近沟道区，从而改善通道中的载流子迁移率，同时不会降低短沟道效应。
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公开(公告)号：US07687354B2
公开(公告)日：2010-03-30
申请号：US12040394
申请日：2008-02-29
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/165 , H01L29/66553 , H01L29/66583 , H01L29/66636 , H01L29/66651 , H01L29/7834 , H01L29/7848
摘要： In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.
摘要翻译： 在半导体制造工艺中，在衬底上形成外延层，其中在外延层和衬底之间存在晶格失配。 形成具有开口的硬掩模覆盖在外延层上。 通过外延层形成凹槽并进入衬底。 凹槽基本上对准硬掩模中的开口。 半导体器件的沟道区形成在凹部中。
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公开(公告)号：US20090221119A1
公开(公告)日：2009-09-03
申请号：US12040394
申请日：2008-02-29
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/165 , H01L29/66553 , H01L29/66583 , H01L29/66636 , H01L29/66651 , H01L29/7834 , H01L29/7848
摘要： In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.
摘要翻译： 在半导体制造工艺中，在衬底上形成外延层，其中在外延层和衬底之间存在晶格失配。 形成具有开口的硬掩模覆盖在外延层上。 通过外延层形成凹槽并进入衬底。 凹槽基本上对准硬掩模中的开口。 半导体器件的沟道区形成在凹部中。
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公开(公告)号：US07544997B2
公开(公告)日：2009-06-09
申请号：US11676114
申请日：2007-02-16
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.
摘要翻译： 一种形成半导体器件的方法包括在半导体器件的源极区域和漏极区域中形成凹部。 该方法还包括在源极区域的凹部中形成第一半导体材料层和在漏极区域的凹部中形成第二半导体材料层，其中第一半导体材料层和第二半导体材料层中的每一个使用应力源 具有第一元素的原子浓度和第二元素的原子浓度的第一比率的材料，其中第一元素是硅，并且掺杂材料的第一浓度水平。 该方法还包括形成覆盖第一半导体材料层和第二半导体材料层的附加半导体材料层，其具有与第一元件和第二元件的原子浓度不同的比率。
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公开(公告)号：US20080197412A1
公开(公告)日：2008-08-21
申请号：US11676114
申请日：2007-02-16
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for forming a semiconductor device includes forming a recess in a source region and a recess in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer in the recess in the source region and a second semiconductor material layer in the recess in the drain region, wherein each of the first semiconductor material layer and the second semiconductor material layer are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers overlying the first semiconductor material layer and the second semiconductor material layer that have a different ratio of the atomic concentration of the first element and the second element.
摘要翻译： 一种形成半导体器件的方法包括在半导体器件的源极区域和漏极区域中形成凹部。 该方法还包括在源极区域的凹部中形成第一半导体材料层和在漏极区域的凹部中形成第二半导体材料层，其中第一半导体材料层和第二半导体材料层中的每一个使用应力源 具有第一元素的原子浓度和第二元素的原子浓度的第一比率的材料，其中第一元素是硅，并且掺杂材料的第一浓度水平。 该方法还包括形成覆盖第一半导体材料层和第二半导体材料层的附加半导体材料层，其具有与第一元件和第二元件的原子浓度不同的比率。
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公开(公告)号：US20070238278A1
公开(公告)日：2007-10-11
申请号：US11278180
申请日：2006-03-31
IPC分类号： H01L21/3205
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L29/6653 , H01L29/66825 , H01L29/66833
摘要： Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions of different heights. In one example, the structure is removed by forming a spacer over the lower portion adjacent to the sidewall of the higher portion. A second material is then formed on the structure outside of the spacer. The spacer is removed and the portion under the spacer is then removed to separate the structure at that location. In one embodiment, separate channel regions are implemented in the separated structures. In other embodiments, separate gate structures are implemented in the separated structures.
摘要翻译： 去除半导体器件中的一部分结构以分离结构。 该结构具有两个不同高度的部分。 在一个示例中，通过在与较高部分的侧壁相邻的下部形成隔离物来移除结构。 然后在间隔件外部的结构上形成第二材料。 移除间隔物，然后移除间隔物下面的部分以在该位置分离结构。 在一个实施例中，在分离的结构中实现单独的通道区域。 在其他实施例中，在分离的结构中实现单独的门结构。
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公开(公告)号：US20080299724A1
公开(公告)日：2008-12-04
申请号：US11756095
申请日：2007-05-31
申请人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
发明人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.
摘要翻译： 一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅电极的侧壁上形成绝缘层; 限定与绝缘层相邻的半导体衬底中的源区和漏区; 在所述半导体衬底的源区和漏区中注入掺杂剂以形成掺杂源极和漏极区; 形成邻近所述绝缘层的侧壁间隔物; 在所述源极和漏极区域中的所述半导体衬底中形成凹部，其中所述凹部直接在所述间隔物的下方延伸距离沟道区域预定的距离; 以及在所述凹部中形成应力源材料。 该方法允许应力源材料形成得更靠近沟道区，从而改善通道中的载流子迁移率，同时不会降低短沟道效应。
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