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公开(公告)号：US07158397B2
公开(公告)日：2007-01-02
申请号：US11024279
申请日：2005-04-14
IPC分类号： G11C5/06
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Line drivers that fit within a specified line pitch. One method of placing line drivers completely underneath a cross point array requires splitting the line driver up so that a portion of the line drivers is on a first side of the cross point array and the other portion is on the opposite side. However, using this technique requires that the width of the drivers is no larger than the width of the memory cells that are being driven. This can be accomplished by stacking transistors such that line drivers fit within a specified line pitch, but are as long as is necessary to include all the necessary circuitry.
摘要翻译： 适合指定线路间距的线路驱动器。 将线驱动器完全放置在交叉点阵列下方的一种方法需要将线驱动器向上分开，使得线驱动器的一部分位于交叉点阵列的第一侧，而另一部分在相对侧。 然而，使用这种技术要求驱动器的宽度不大于被驱动的存储单元的宽度。 这可以通过堆叠晶体管来实现，使得线路驱动器适合指定的线间距，但是必须包括所有必要的电路。
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公开(公告)号：US20060245241A1
公开(公告)日：2006-11-02
申请号：US11478520
申请日：2006-06-29
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2213/31 , G11C2213/71 , G11C2213/77
摘要： A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.
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43.发明授权Non-volatile memory with a single transistor and resistive memory element 失效具有单个晶体管和电阻式存储器元件的非易失性存储器公开(公告)号：US07126841B2
公开(公告)日：2006-10-24
申请号：US11061101
申请日：2005-02-18
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C2213/31 , G11C2213/79 , H01L27/11502 , H01L27/11507 , H01L27/2409 , H01L27/2436 , H01L27/2445 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.
摘要翻译： 每个存储单元具有单个半导体器件的非易失性存储器单元。 本发明通常允许在支撑半导体器件的半导体衬底上形成多个存储单元。 通常在非常高的温度下，在衬底上方形成在施加电压脉冲时改变其电阻状态在低电阻状态和高电阻状态之间的多电阻状态材料层。 虽然在衬底和多电阻状态材料之间制造的层使用可承受高温处理的材料，但是在多电阻状态材料之上制造的层不需要经受高温处理。
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公开(公告)号：US07054183B2
公开(公告)日：2006-05-30
申请号：US11218655
申请日：2005-09-02
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3468 , G11C2013/0066 , G11C2213/31
摘要： A programming circuit is provided. As a conductive memory cell is programmed, its resistance changes. The provided programming circuit monitors the changing resistance while programming the memory cell. The programming circuit can be used to only program the memory cell for as long as programming is actually needed. Additionally, the programming circuit can be used to only program the memory cell when it has a value that needs to be changed.
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公开(公告)号：US07020006B2
公开(公告)日：2006-03-28
申请号：US10922202
申请日：2004-08-18
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： Circuitry that discharges conductive array lines is provided. Generally, the conductive array lines are simultaneously selected and apply an appropriate programming pulse. Accordingly, the conductive array lines need to be discharged in connection with a write operation. The discharge can occur either prior to or following a write operation.
摘要翻译： 提供放电导电阵列线路的电路。 通常，同时选择导电阵列线并施加适当的编程脉冲。 因此，导电阵列线需要与写入操作相关地放电。 放电可以在写入操作之前或之后发生。
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46.发明申请公开(公告)号：US20060007769A1
公开(公告)日：2006-01-12
申请号：US11218655
申请日：2005-09-02
IPC分类号： G11C7/02
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3468 , G11C2013/0066 , G11C2213/31
摘要： A programming circuit is provided. As a conductive memory cell is programmed, its resistance changes. The provided programming circuit monitors the changing resistance while programming the memory cell. The programming circuit can be used to only program the memory cell for as long as programming is actually needed. Additionally, the programming circuit can be used to only program the memory cell when it has a value that needs to be changed.
摘要翻译： 提供了编程电路。 由于导电存储单元被编程，其电阻变化。 所提供的编程电路在编程存储器单元时监视变化的电阻。 只要编程实际需要，编程电路就可以用于只对存储单元进行编程。 此外，编程电路可以用于仅当存储单元具有需要改变的值时对其进行编程。
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47.发明授权Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权本地位线及其选择方法可以访问交叉点阵列中的存储器元件公开(公告)号：US08897050B2
公开(公告)日：2014-11-25
申请号：US13588461
申请日：2012-08-17
CPC分类号： G11C5/025 , G11C5/02 , G11C8/00 , G11C11/00 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2213/77 , H01L21/82 , H01L27/2481 , H01L45/16
摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
摘要翻译： 实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。 在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。 交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。 每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。 还包括设置在X线的子集和Y线部分的组之间的存储器元件。 在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。
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公开(公告)号：US08737151B2
公开(公告)日：2014-05-27
申请号：US13252934
申请日：2011-10-04
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C7/12 , G11C7/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0045 , G11C2013/0054 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/71 , G11C2213/77
摘要： A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
摘要翻译： 用于存储器的低读取当前体系结构。 允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。
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49.发明授权公开(公告)号：US07372753B1
公开(公告)日：2008-05-13
申请号：US11583676
申请日：2006-10-19
IPC分类号： G11C7/02
CPC分类号： G11C11/16 , G11C13/004 , G11C2013/0057
摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
摘要翻译： 双端存储器阵列包括多个第一和第二导电迹线。 地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。 在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读操作中由感测单元感测。 总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。 电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。
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50.发明申请公开(公告)号：US20080094929A1
公开(公告)日：2008-04-24
申请号：US11583676
申请日：2006-10-19
CPC分类号： G11C11/16 , G11C13/004 , G11C2013/0057
摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
摘要翻译： 双端存储器阵列包括多个第一和第二导电迹线。 地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。 在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读操作中由感测单元感测。 总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。 电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。
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