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公开(公告)号：US07443759B1
公开(公告)日：2008-10-28
申请号：US11740892
申请日：2007-04-26
CPC分类号： G11C11/413 , G06F12/0895 , G06F2212/1028 , G11C7/20 , G11C8/14 , Y02D10/13
摘要： A reduced-power memory (such as for a cache memory system of a processor or a microprocessor) provides per-sector ground control to advantageously reduce power consumption. Selective power control of a plurality of sectors comprised in the reduced-power memory is responsive to a subset of address bits for accessing the memory. The selective power control individually powers-up a selected one of the sectors in response to an access, and then powers-down the selected sector when the access is complete. The power-up is via a decrease in ground potential from a retention level to an access level. Time needed to vary the ground potential is optionally masked by providing address information used by the selective power control in advance of providing other address information. For example, in a cache, a tag access is overlapped with power-up of a selected sector, thus masking latency of powering up the selected sector.
摘要翻译： 降低功率的存储器（例如用于处理器或微处理器的高速缓冲存储器系统）提供每扇区地面控制以有利地降低功耗。 包含在所述降低功率存储器中的多个扇区的选择性功率控制响应于访问所述存储器的地址位的子集。 响应于访问，选择性功率控制单独地加电所选扇区中的一个扇区，然后在访问完成时关闭所选择的扇区。 上电是通过从保持级别到访问级别的地电位降低。 通过在提供其他地址信息之前提供由选择性功率控制使用的地址信息，可选地掩蔽了改变地电位所需的时间。 例如，在高速缓存中，标签访问与所选择的扇区的加电重叠，从而掩蔽对选定扇区加电的等待时间。
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公开(公告)号：US07389408B1
公开(公告)日：2008-06-17
申请号：US11566206
申请日：2006-12-01
IPC分类号： G06F7/76
CPC分类号： G06F9/30178 , G06F9/30149 , G06F9/30156 , G06F9/30167 , G06F9/3808 , G06F9/3832 , G06F9/3836
摘要： An instruction stream having variable length instructions with embedded constants (e.g. immediate values and displacements) is translated into a stream of operations and a corresponding stream of bit fields, enabling advantageous compact storage of the embedded constants. The operations and the compact constants are optionally stored in entries in a trace cache and/or processed by execution pipelines. The compact constants are optionally formulated as a small constant field, a pointer, or both. The pointer of a particular one of the operations optionally references one of the bit fields within a window of the operations associated with the particular operation. A full-sized constant is constructed from one or more contiguous ones of the bit fields, starting with the referenced bit field, by unpacking and uncompressing information from the contiguous bit fields. An operation optionally includes a plurality of small constant fields and pointers to specify a respective plurality of constants.
摘要翻译： 具有嵌入常数（例如立即值和位移）的具有可变长度指令的指令流被转换成操作流和相应的位字段，从而实现嵌入常数的有利的紧凑存储。 操作和紧凑常数可选地存储在跟踪缓存中的条目和/或由执行管线处理。 紧凑常数可选地被制定为小常数场，指针或两者。 特定操作之一的指针可选地引用与特定操作相关联的操作的窗口内的一个位字段。 通过解码和解压缩来自连续位字段的信息，从引用的位字段开始，从一个或多个连续的位字段构造全尺寸常数。 操作可选地包括多个小常数场和指针，以指定相应的多个常数。
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公开(公告)号：US07389403B1
公开(公告)日：2008-06-17
申请号：US11277761
申请日：2006-03-29
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/30181 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： An Adaptive Computing Ensemble (ACE) includes a plurality of flexible computation units as well as an execution controller to allocate the units to Computing Ensembles (CEs) and to assign threads to the CEs. The units may be any combination of ACE-enabled units, including instruction fetch and decode units, integer execution and pipeline control units, floating-point execution units, segmentation units, special-purpose units, reconfigurable units, and memory units. Some of the units may be replicated, e.g. there may be a plurality of integer execution and pipeline control units. Some of the units may be present in a plurality of implementations, varying by performance, power usage, or both. The execution controller dynamically alters the allocation of units to threads in response to changing performance and power consumption observed behaviors and requirements. The execution controller also dynamically alters performance and power characteristics of the ACE-enabled units, according to the observed behaviors and requirements.
摘要翻译： 自适应计算集合（ACE）包括多个灵活的计算单元以及将单元分配给计算集合（CE）并将线程分配给CE的执行控制器。 单元可以是启用ACE的单元的任何组合，包括指令提取和解码单元，整数执行和流水线控制单元，浮点执行单元，分段单元，专用单元，可重配置单元和存储单元。 一些单位可能被复制，例如 可以存在多个整数执行和流水线控制单元。 一些单元可以存在于由性能，功率使用或两者变化的多个实现中。 响应于观察到的行为和要求的性能和功耗的变化，执行控制器动态地改变单元对线程的分配。 执行控制器还根据观察到的行为和要求动态地改变启用ACE的单元的性能和功率特性。
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44.发明申请BROADCAST MESSAGING AND ACKNOWLEDGMENT MESSAGING FOR POWER MANAGEMENT IN A MULTIPROCESSOR SYSTEM 有权用于多处理器系统中的电源管理的广播消息传递和确认消息公开(公告)号：US20140281275A1
公开(公告)日：2014-09-18
申请号：US13799268
申请日：2013-03-13
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , G06F1/3243 , G06F2212/1028 , Y02D10/13
摘要： Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor.
摘要翻译： 各个方面提供了实现高速缓存一致性协议。 系统包括至少一个处理部件和集中控制器。 所述至少一个处理组件包括高速缓存控制器。 高速缓存控制器被配置为管理与处理器相关联的高速缓冲存储器。 集中控制器被配置为基于处理器的功率状态与高速缓存控制器进行通信。
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45.发明授权Data cache rollbacks for failed speculative traces with memory operations 有权具有内存操作的失败的推测性跟踪的数据高速缓存回滚公开(公告)号：US08370609B1
公开(公告)日：2013-02-05
申请号：US12030854
申请日：2008-02-13
IPC分类号： G06F9/312
CPC分类号： G06F9/3808 , G06F9/3834 , G06F9/3863 , G06F11/3636
摘要： This invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Memory operation ordering entries correspond to each one of the active memory operations. Violations of the ordering constraints result in overwriting the checkpoint locations associated with the selected trace as well as the checkpoint locations associated with traces that are younger than the selected trace.
摘要翻译： 本发明包括用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 检查点条目与每个跟踪相关联。 每个条目指的是检查点位置。 存储器操作排序条目对应于每个活动存储器操作。 违反排序限制导致覆盖与所选跟踪相关联的检查点位置以及与所选跟踪较年轻的跟踪关联的检查点位置。
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公开(公告)号：US08225315B1
公开(公告)日：2012-07-17
申请号：US11933319
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.
摘要翻译： 一种包括物理核心和第一虚拟核心的虚拟核心管理系统，包括与执行第一程序相关联的逻辑状态的集合。 第一个虚拟内核映射到物理内核。 虚拟核心管理系统还包括第二虚拟核心，其包括与执行第二程序相关联的逻辑状态的集合，虚拟核心管理组件被配置为从物理核心取消映射第一虚拟核心并将第二虚拟核心映射到 响应虚拟核心管理组件检测物理内核空闲的物理核心。
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公开(公告)号：US07966479B1
公开(公告)日：2011-06-21
申请号：US11880859
申请日：2007-07-23
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , G06F9/3017 , G06F9/30189 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/1027 , G06F12/1054
摘要： An instruction processing circuit includes a decoder circuit, a basic block builder circuit, a multi-block builder circuit, first and second predictor circuits, and a sequencer circuit, where the sequencer circuit is operable, in a first environment, to cause the first predictor circuit to generate a prediction for a particular conditional branch op concurrently with the second predictor circuit generating a prediction for another particular conditional branch op, where the sequencer circuit is also operable, in a second environment, to cause the first predictor circuit to generate a prediction for the particular conditional branch op sequentially with the second predictor circuit generating a prediction for the another particular conditional branch operation.
摘要翻译： 指令处理电路包括解码器电路，基本块构建器电路，多块构建器电路，第一和第二预测器电路和定序器电路，其中定序器电路在第一环境中可操作以使第一预测器 电路，用于与第二预测器电路同时产生用于特定条件分支运算的预测，以产生另一特定条件分支op的预测，其中定序器电路在第二环境中也可操作，以使第一预测电路产生预测 对于特定条件分支，顺序地与第二预测器电路产生对另一特定条件分支操作的预测。
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48.发明授权Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder 有权跟踪单元，具有来自解码器（旁路模式）和基本块构建器的操作路径公开(公告)号：US07953961B1
公开(公告)日：2011-05-31
申请号：US11880863
申请日：2007-07-23
IPC分类号： G06F9/40
CPC分类号： G06F9/30061 , G06F9/3802 , G06F9/3808 , G06F9/3836
摘要： An instruction processing circuit for a processor includes a decoder circuit, a cache circuit, a sequencer circuit operable to select a next sequence of operations, and an operations fetch circuit operable to convey the next sequence of operations to an execution circuit, receive an indication that a sequencing action of the sequencer circuit is sequencing ahead of the execution circuit, and switch, based on the indication, a source of the operations fetch circuit between the cache circuit and the decoder circuit.
摘要翻译： 用于处理器的指令处理电路包括解码器电路，高速缓存电路，可操作以选择下一个操作序列的定序器电路，以及可操作以将下一个操作序列传送到执行电路的操作提取电路，接收指示 定序器电路的排序动作在执行电路之前排序，并且基于指示，在高速缓存电路和解码器电路之间切换操作提取电路的源。
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公开(公告)号：US07949854B1
公开(公告)日：2011-05-24
申请号：US11880861
申请日：2007-07-23
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/0875 , G06F12/1027 , G06F12/1054
摘要： An instruction processing unit includes a trace builder circuit operable to (i) receive at least a portion of a first type of sequence of operations and to generate, based thereon, a second type of sequence of operations, where the portion includes at most one control transfer instruction that, when present, ends the portion, (ii) receive sets of at least two sequences of operations and to generate, based thereon, a plurality of third type of sequences of operations, where a sequence of operations of the third type includes one or more interior control transfer instructions and is generated from the sequence of operations of the second type and another sequence of operations of the third type, and (iii) retrieve the sequence of operations of the second type and the another sequence of operations of the third type from a cache circuit.
摘要翻译： 指令处理单元包括跟踪构建器电路，其可操作以（i）接收第一类型的操作序列的至少一部分并且基于此产生第二类型的操作序列，其中该部分至多包括一个控制 传送指令，当存在时结束部分，（ii）接收至少两个操作序列的集合，并且基于此生成多个第三类型的操作序列，其中第三类型的操作序列包括 一个或多个内部控制传送指令，并且从第二类型的操作序列和第三类型的另一操作序列生成，以及（iii）检索第二类型的操作序列和第二类操作的另一操作序列 第三种类型从缓存电路。
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公开(公告)号：US07849292B1
公开(公告)日：2010-12-07
申请号：US11941900
申请日：2007-11-16
申请人： Matthew William Ashcraft , John Gregory Favor , Christopher Patrick Nelson , Ivan Pavle Radivojevic , Joseph Byron Rowlands , Richard Win Thaik
发明人： Matthew William Ashcraft , John Gregory Favor , Christopher Patrick Nelson , Ivan Pavle Radivojevic , Joseph Byron Rowlands , Richard Win Thaik
IPC分类号： G06F9/00
CPC分类号： G06F9/3853 , G06F8/45 , G06F9/3017 , G06F9/3808 , G06F9/3836
摘要： A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include locating an operation, if any, that is next within the sequence of operations and setting a current operation to be that operation. The current operation is processed as follows: a) de-activating, if not already de-activated, a consumed indicator associated with the current operation; and b) when the current operation is of the producer type, then activating, if not already activated, a producer indicator associated with the current operation, and locating a first set of operations, if any, that i) are earlier in the sequence of operations than the current operation, ii) have their associated producer indicator activated, and iii) have their associated consumed indicator de-activated, and then de-activating the producer indicator associated with each operation in the first set. When the current operation is of the consumer type, then locating a second set of operations, if any, that are earlier in the sequence of operations than the current operation, and then activating, if not already activated, the consumed indicator associated with each operation in the second set.
摘要翻译： 公开了一种用于优化适于由处理器执行的操作序列的方法和装置，以包括定位接下来在操作序列内的操作（如果有的话），并将当前操作设置为该操作。 当前操作如下处理：a）取消激活与当前操作相关联的消耗的指示符（如果尚未被去激活） 以及b）当当前操作是生产者类型时，然后激活（如果尚未激活）与当前操作相关联的生产者指示符，并且定位第一组操作（如果有的话）i） 操作，ii）使其相关联的生成器指示符被激活，以及iii）使其相关联的消费指示符被激活，然后去激活与第一组中的每个操作相关联的生成器指示符。 当当前操作是消费者类型时，然后找到比当前操作更早的操作序列中的第二组操作（如果有的话），然后激活（如果尚未激活）与每个操作相关联的消耗的指示符 在第二集。
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