公开(公告)号：US08271730B2

公开(公告)日：2012-09-18

申请号：US11907265

申请日：2007-10-10

申请人： Frederic Claude Marie Piry ,  Philippe Jean-Pierre Raphalen ,  Norbert Bernard Eugéne Lataille ,  Stuart David Biles ,  Richard Roy Grisenthwaite

发明人： Frederic Claude Marie Piry ,  Philippe Jean-Pierre Raphalen ,  Norbert Bernard Eugéne Lataille ,  Stuart David Biles ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： A plurality of processing units for performing data processing operations require access to data in shared memory. Each has an associated cache storing a subset of the data for access by that processing unit. A cache coherency protocol ensures data accessed by each unit is up-to-date. Each unit issues a write access request when outputting a data value for storing in shared memory. When the write access request requires both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic. The coherency operation is performed for all of the caches including the cache associated with the processing unit that issued the write access request in order to ensure that the data in those caches is kept coherent.

摘要翻译： 用于执行数据处理操作的多个处理单元需要访问共享存储器中的数据。 每个具有存储用于该处理单元访问的数据的子集的相关联的高速缓存。 缓存一致性协议确保每个单元访问的数据是最新的。 当输出用于存储在共享存储器中的数据值时，每个单元发出写访问请求。 当写访问请求需要更新相关联的高速缓存和共享存储器时，在高速缓存一致性逻辑内启动一致性操作。 对于包括与发出写访问请求的处理单元相关联的缓存的所有缓存执行一致性操作，以便确保这些高速缓存中的数据保持一致。

公开(公告)号：US07805595B2

公开(公告)日：2010-09-28

申请号：US11785918

申请日：2007-04-20

申请人： Emre Özer ,  Alastair David Reid ,  Stuart David Biles

发明人： Emre Özer ,  Alastair David Reid ,  Stuart David Biles

IPC分类号： G06F9/00

CPC分类号： G06F9/3844 ,  G06F9/383 ,  G06F9/3832 ,  G06F12/0862 ,  G06F12/122

摘要： A data processing apparatus has processing circuitry for performing processing operations including high priority operations and low priority operations, events occurring during performance of those processing operations. Prediction circuitry includes a history storage having a plurality of counter entries for storing count values, and index circuitry for identifying, dependent on the received event, at least one counter entry and for causing the history storage to output the count value stored in that at least one counter entry, with the prediction data being derived from the output count value. Update control circuitry modifies at least one count value stored in the history storage in response to update data generated by the processing circuitry. The update control circuitry has a priority dependent modification mechanism such that the modification is dependent on the priority of the processing operation with which that update data is associated.

摘要翻译： 数据处理装置具有用于执行包括高优先级操作和低优先级操作的处理操作的处理电路，以及在执行这些处理操作期间发生的事件。 预测电路包括具有用于存储计数值的多个计数器条目的历史存储器和用于根据接收到的事件来识别至少一个计数器条目并用于使历史存储器输出存储在该至少一个计数器中的计数值的索引电路 一个计数器条目，其中预测数据从输出计数值导出。 响应于由处理电路产生的更新数据，更新控制电路修改存储在历史存储器中的至少一个计数值。 更新控制电路具有优先级相关的修改机制，使得修改取决于与该更新数据相关联的处理操作的优先级。

公开(公告)号：US07707390B2

公开(公告)日：2010-04-27

申请号：US11790483

申请日：2007-04-25

申请人： Emre Özer ,  Vladimir Vasekin ,  Stuart David Biles

发明人： Emre Özer ,  Vladimir Vasekin ,  Stuart David Biles

IPC分类号： G06F9/00

CPC分类号： G06F9/3851 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384

摘要： A multi-threaded in-order superscalar processor 2 is described having a fetch stage 8 within which thread interleaving circuitry 36 interleaves instructions taken from different program threads to form an interleaved stream of instructions which is then decoded and subject to issue. Hint generation circuitry 62 within the fetch stage 8 adds hint data to the threads indicating that parallel issue of an associated instruction is permitted with one of more other instructions.

摘要翻译： 描述了具有提取级8的多线程顺序超标量处理器2，线程交织电路36交织来自不同节目线程的指令，以形成交织的指令流，然后解码并发生问题。 提取阶段8内的提示生成电路62向线程添加提示数据，指示相关指令的并行发行被许多其他指令之一允许。

公开(公告)号：US20090222625A1

公开(公告)日：2009-09-03

申请号：US11990394

申请日：2005-09-13

申请人： Mrinmoy Ghosh ,  Emre Özer ,  Stuart David Biles

发明人： Mrinmoy Ghosh ,  Emre Özer ,  Stuart David Biles

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/383 ,  G06F12/0802 ,  G06F12/0897

摘要： A data processing apparatus and method are provided for detecting cache misses. The data processing apparatus has processing logic for executing a plurality of program threads, and a cache for storing data values for access by the processing logic. When access to a data value is required while executing a first program thread, the processing logic issues an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure to determine whether the data value is stored in the cache. Indication logic is provided which in response to an address portion of the address provides an indication as to whether the data value is stored in the cache, this indication being produced before a result of the lookup procedure is available, and the indication logic only issuing an indication that the data value is not stored in the cache if that indication is guaranteed to be correct. Control logic is then provided which, if the indication indicates that the data value is not stored in the cache, uses that indication to control a process having an effect on a program thread other than the first program thread.

摘要翻译： 提供了一种用于检测高速缓存未命中的数据处理装置和方法。 数据处理装置具有用于执行多个程序线程的处理逻辑，以及用于存储由处理逻辑进行访问的数据值的高速缓存。 当执行第一程序线程时需要访问数据值时，处理逻辑发出指定与该数据值相关联的存储器中的地址的访问请求，并且高速缓冲存储器响应于该地址执行查找过程以确定是否 数据值存储在缓存中。 指示逻辑被提供，其响应于地址的地址部分提供关于数据值是否存储在高速缓存中的指示，该指示是在查找过程的结果可用之前产生的，并且指示逻辑仅发出 指示如果该指示保证正确，则数据值不存储在高速缓存中。 然后提供控制逻辑，如果该指示指示数据值未被存储在高速缓存中，则使用该指示来控制对除第一程序线程之外的程序线程有影响的进程。

公开(公告)号：US20090031082A1

公开(公告)日：2009-01-29

申请号：US12224725

申请日：2006-03-06

申请人： Simon Andrew Ford ,  Mrinmoy Ghosh ,  Emre Ozer ,  Stuart David Biles

发明人： Simon Andrew Ford ,  Mrinmoy Ghosh ,  Emre Ozer ,  Stuart David Biles

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0864 ,  G06F2212/1016 ,  G06F2212/6032 ,  Y02D10/13

摘要： A data processing apparatus is provided having processing logic for performing a sequence of operations, and a cache having a plurality of segments for storing data values for access by the processing logic. The processing logic is arranged, when access to a data value is required, to issue an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure during which it is determined whether the data value is stored in the cache. Indication logic is provided which, in response to an address portion of the address, provides for each of at least a subject of the segments an indication as to whether the data value is stored in that segment. The indication logic has guardian storage for storing guarding data, and hash logic for performing a hash operation on the address portion in order to reference the guarding data to determine each indication. Each indication indicates whether the data value is either definitely not stored in the associated segment or is potentially stored with the associated segment, and the cache is then operable to use the indications produced by the indication logic to affect the lookup procedure performed in respect of any segment whose associated indication indicates that the data value is definitely not stored in that segment. This technique has been found to provide a particularly power efficient mechanism for accessing the cache.

摘要翻译： 提供了具有用于执行操作序列的处理逻辑的数据处理装置，以及具有多个段的高速缓存，用于存储由处理逻辑进行访问的数据值。 当需要访问数据值时，处理逻辑被布置为发出指定与该数据值相关联的存储器中的地址的访问请求，并且高速缓存响应于地址以执行查找过程，在该过程中确定是否 数据值存储在缓存中。 提供指示逻辑，响应于地址的地址部分，为段中的至少一个对象提供关于数据值是否存储在该段中的指示。 指示逻辑具有用于存储保护数据的保护存储和用于对地址部分执行散列操作的散列逻辑，以引用保护数据来确定每个指示。 每个指示指示数据值是否绝对不存储在相关联的段中或潜在地与相关联的段相关联，并且高速缓存然后可操作地使用由指示逻辑产生的指示来影响关于任何 其相关联的指示表明数据值绝对不存储在该段中。 已经发现这种技术提供了用于访问高速缓存的特别有效的机构。

公开(公告)号：US20080295105A1

公开(公告)日：2008-11-27

申请号：US12149772

申请日：2008-05-08

申请人： Emre Ozer ,  Stuart David Biles

发明人： Emre Ozer ,  Stuart David Biles

IPC分类号： G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/5011 ,  G06F2209/5021 ,  G06F2209/507

摘要： A data processing apparatus and method are provided for managing multiple program threads executed by processing circuitry. The multiple program threads include at least one high priority program thread and at least one lower priority program thread. At least one storage unit is shared between the multiple program threads and has multiple entries for storing information for reference by the processing circuitry when executing the program threads. Thread control circuitry is used to detect a condition indicating an adverse effect caused by a lower priority program thread being executed by the processing circuitry and resulting from sharing of the at least one storage unit between the multiple program threads. On detection of such a condition, the thread control circuitry issues an alert signal, and a scheduler is then responsive to the alert signal to cause execution of the lower priority program thread causing the adverse effect to be temporarily halted, for example by causing that lower priority program thread to be de-allocated and an alternative lower priority program thread allocated in its place. This has been found to provide a particularly efficient mechanism for allowing any high priority program thread to progress as much as possible, whilst at the same time improving the overall processor throughput by seeking to find co-operative lower priority program threads.

摘要翻译： 提供了一种用于管理由处理电路执行的多个程序线程的数据处理装置和方法。 多个程序线程包括至少一个高优先级程序线程和至少一个较低优先级的程序线程。 在多个程序线程之间共享至少一个存储单元，并且具有用于存储信息的多个条目，供执行程序线程时由处理电路参考。 线程控制电路用于检测指示由处理电路执行的较低优先级程序线程引起的不利影响的状况，并且由多个程序线程之间的至少一个存储单元的共享产生。 在检测到这种情况时，线程控制电路发出报警信号，并且调度器然后对报警信号作出响应，从而导致低优先级程序线程的执行，从而导致不利影响被暂时停止，例如通过使得较低 要重新分配的优先级程序线程和分配给其的替代低优先级程序线程。 已经发现，这提供了一种特别有效的机制，用于允许任何高优先级的程序线程尽可能地进行，同时通过寻求找到合作的较低优先级的程序线程来提高整体处理器的吞吐量。

公开(公告)号：US07343482B2

公开(公告)日：2008-03-11

申请号：US11048663

申请日：2005-01-31

申请人： Stuart David Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

发明人： Stuart David Biles ,  Krisztian Flautner ,  Scott Mahlke ,  Nathan Clark

IPC分类号： G06F9/00

CPC分类号： G06F8/4441

摘要： There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said program, said apparatus comprising: a memory operable to store a program formed of separate program instructions; processing logic operable to execute respective separate program instructions from said program; and accelerator logic operable in response to reaching an execution point within said program associated with a subgraph suggestion to execute a sequence of program instructions corresponding to said subgraph suggestion as an accelerated operation instead of executing said sequence of program instructions as respective separate program instructions with said processing logic.

摘要翻译： 提供了一种用于在具有程序指令和子图建议信息的程序的控制下处理数据的装置，该子图表建议信息识别与所述程序中识别的计算子图相对应的程序指令的相应序列，所述装置包括：存储器，可操作以存储由单独程序形成的程序 说明书 处理逻辑可操作以从所述程序执行相应的单独的程序指令; 以及加速器逻辑，其可操作以响应于到达与子图建议相关联的所述程序内的执行点，以执行对应于所述子图建议的程序指令序列作为加速操作，而不是执行所述程序指令序列作为具有所述 处理逻辑。

公开(公告)号：US20080040592A1

公开(公告)日：2008-02-14

申请号：US11501920

申请日：2006-08-10

申请人： Vladimir Vasekin ,  Stuart David Biles ,  Andrew Christopher Rose ,  Wilco Dijkstra

发明人： Vladimir Vasekin ,  Stuart David Biles ,  Andrew Christopher Rose ,  Wilco Dijkstra

IPC分类号： G06F15/00

CPC分类号： G06F12/0875 ,  G06F9/30058 ,  G06F9/30181 ,  G06F9/3806 ,  G06F12/0862 ,  G06F2212/6028 ,  Y02D10/13

摘要： A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10 or both, is used to store branch target addresses or blocks of instructions starting at the branch target respectively. A control circuit 12 is responsive to the contents of the instruction queue 4 when a branch instruction is encountered to determine whether or not storage resources within the branch target cache 8, 10 should be allocated to that branch instruction. Storage resources within the branch target cache 8, 10 will be allocated when the number of program instructions within the instruction queue is below a threshold number and/or the estimated execution time of the program instructions is below a threshold time.

摘要翻译： 数据处理系统包括指令提取电路2，指令队列4和其他处理电路6。 分支目标高速缓存（分支目标地址高速缓存8，分支目标指令高速缓存10或两者）分别用于存储从分支目标开始的分支目标地址或指令块。 当遇到分支指令时，控制电路12响应于指令队列4的内容，以确定分支目标高速缓存8,10中的存储资源是否应被分配给该分支指令。 当指令队列内的程序指令数量低于阈值数量和/或程序指令的估计执行时间低于阈值时间时，将分配分支目标缓存器8,10内的存储资源。

公开(公告)号：US20070288735A1

公开(公告)日：2007-12-13

申请号：US11449858

申请日：2006-06-09

申请人： Vladimir Vasekin ,  Stuart David Biles ,  Yuri Levdik ,  Andrei Kapustin

发明人： Vladimir Vasekin ,  Stuart David Biles ,  Yuri Levdik ,  Andrei Kapustin

IPC分类号： G06F9/00

CPC分类号： G06F9/3851 ,  G06F9/30101 ,  G06F9/3848

摘要： A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thread. Different mappings are used between preceding branch behaviour and the prediction value stored within respective branch history registers 20, 22. These different mappings may be provided by inverters placed into the shift in paths for the branch history registers 20, 22 or by adders 40, 42 or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table 18 such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behaviour.

摘要翻译： 具有硬件调度逻辑6,8,10,12的多线程处理器内的分支预测机制16,18使用共享全局历史表18，该共享全局历史表18由各个分支历史寄存器20,22针对每个程序线索引。 在之前的分支行为与存储在相应分支历史寄存器20,22内的预测值之间使用不同的映射。 这些不同的映射可以由放置在用于分支历史寄存器20,22的路径中的变换器或由加法器40,42或以某种其他方式提供。 不同的映射有助于使全局历史表18中的特定存储位置的使用概率相等，使得多个程序线程对于与先前分支行为的更常见的模式相对应的相同存储位置不会过度竞争。

公开(公告)号：US07162590B2

公开(公告)日：2007-01-09

申请号：US10788315

申请日：2004-03-01

申请人： Julie-Anne Francoise Marie Pruvost ,  Norbert Bernard Eugene Lataille ,  Stuart David Biles

发明人： Julie-Anne Francoise Marie Pruvost ,  Norbert Bernard Eugene Lataille ,  Stuart David Biles

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0831

摘要： Within a coherent multi-processing system multiple processor cores 4, 6 are coupled via respective memory buses to a memory access control unit 16. The memory buses are formed of a uni-processing portion containing signals specifying a memory access request in accordance with a uni-processing protocol. This uni-processing bus is augmented by a multi-processing bus containing signals giving additional information concerning memory access requests which may be used by the memory access control unit to service those requests and manage coherency within the system.

摘要翻译： 在相干多处理系统中，多个处理器核心4,6通过相应的存储器总线耦合到存储器访问控制单元16。 存储器总线由根据单处理协议的包含指定存储器访问请求的信号的单处理部分形成。 这种单处理总线由包含信号的多处理总线增加，该信号提供关于存储器访问请求的附加信息，存储器访问控制单元可以由存储器访问控制单元使用来为这些请求提供服务并且管理系统内的一致性。