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公开(公告)号：US07344983B2
公开(公告)日：2008-03-18
申请号：US10907061
申请日：2005-03-18
申请人： Sadanand V. Deshpande , Ying Li , Kevin E. Mello , Renee T. Mo , Wesley C. Natzle , Kirk D. Peterson , Robert J. Purtell
发明人： Sadanand V. Deshpande , Ying Li , Kevin E. Mello , Renee T. Mo , Wesley C. Natzle , Kirk D. Peterson , Robert J. Purtell
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , C23C16/0227 , H01L21/02057 , H01L21/28512 , H01L21/67207 , H01L21/67745
摘要： A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.
摘要翻译： 提供了一种集群工具，用于实现半导体器件表面的集群和集成表面预清洁。 更具体地，提供了一种集成工具及其在集成半导体器件表面预清洁中的应用方法，其针对制造方面，其中用于在半导体上执行干法处理化学氧化物去除（COR）的室 器件表面与诸如用于硅化物或接触形成的金属沉积工具的其它工具聚集，包括在簇工具中提供真空转移模块。
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42.发明授权公开(公告)号：US06221775B1
公开(公告)日：2001-04-24
申请号：US09159699
申请日：1998-09-24
申请人： Thomas G. Ference , William F. Landers , Michael J. MacDonald , Walter E. Mlynko , Mark P. Murray , Kirk D. Peterson
发明人： Thomas G. Ference , William F. Landers , Michael J. MacDonald , Walter E. Mlynko , Mark P. Murray , Kirk D. Peterson
IPC分类号： H01L21302
CPC分类号： H01L21/7684 , H01L21/3212
摘要： A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.
摘要翻译： 平面化半导体衬底的表面的工艺。 该过程通过在半导体衬底的表面上形成图案化的凸起和凹陷区域开始。 然后在图案化的凸起和凹陷区域上形成一层材料。 对该层进行化学机械平坦化（CMP）工艺步骤，直到所有凸起区域至少部分地从层中去除。 最后，用反应离子蚀刻（RIE）工艺蚀刻抛光衬底的表面。
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43.发明授权3-dimensional integrated circuit testing using MEMS switches with tungsten cone contacts 有权使用具有钨锥触点的MEMS开关的三维集成电路测试公开(公告)号：US08791712B2
公开(公告)日：2014-07-29
申请号：US13364345
申请日：2012-02-02
IPC分类号： G01R1/067
CPC分类号： G01R1/06727 , B81B2203/0118 , B81C1/00111 , G01R1/06738 , G01R1/06744 , G01R1/07342 , G01R3/00 , H01L21/76804 , H01L21/76885 , H01L22/14 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).
摘要翻译： 一种用于测试多层三维集成电路（IC）的测试系统，其中临时连接两个独立的IC电路层以实现功能性，包括具有三维IC的第一部分的被测芯片，以及 测试探针芯片，其具有第三部分的IC和微机电系统（MEMS）开关，其选择性地完成第一IC层中的第三部分的第三部分之间的功能电路和第二部分内的电路 的三维IC在第二IC层中。 MEMS开关包括钨（W）锥形触点，其使得被测芯片的电路和测试探针芯片之间的选择性电接触，并且使用梯度硼磷硅酸盐玻璃（BPSG）的模板形成。
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公开(公告)号：US20130285193A1
公开(公告)日：2013-10-31
申请号：US13457601
申请日：2012-04-27
CPC分类号： H01L28/40 , H01L21/84 , H01L27/1203 , H01L28/91 , H01L29/66181 , H01L29/945
摘要： A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.
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公开(公告)号：US20130084476A1
公开(公告)日：2013-04-04
申请号：US13252366
申请日：2011-10-04
CPC分类号： H01M10/04 , H01M2/204 , H01M2/24 , H01M2/34 , H01M4/767 , H01M10/02 , H01M10/052 , H01M10/0562 , H01M10/42 , Y02E60/12 , Y10T29/49108
摘要： A solid-state battery structure having a plurality of battery cells formed in a substrate, method of manufacturing the same and design structure thereof are provided. The battery structure includes a patterned cathode electrode layer formed upon the substrate and structured to form a plurality of sub-arrays of the battery cells. The battery structure further includes a plurality of fuse wires structured to interconnect at least two adjacent sub-arrays. At least one of the plurality of fuse wires is structured to be blown to disconnect an interconnection having a defective sub-array. Advantageously, the plurality of fuse wires is an integral part of the battery structure.
摘要翻译： 提供了具有形成在基板中的多个电池单元的固态电池结构，其制造方法和设计结构。 电池结构包括形成在基板上并构造成形成电池单元的多个子阵列的图案化阴极电极层。 电池结构还包括构造成互连至少两个相邻子阵列的多个熔丝。 多个熔丝中的至少一个被构造成被吹塑以断开具有缺陷子阵列的互连。 有利的是，多个熔丝是电池结构的组成部分。
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46.发明申请公开(公告)号：US20120245724A1
公开(公告)日：2012-09-27
申请号：US13052346
申请日：2011-03-21
申请人： Mete Erturk , Ezra D.B. Hall , Kirk D. Peterson
发明人： Mete Erturk , Ezra D.B. Hall , Kirk D. Peterson
CPC分类号： H01L22/14 , H01L22/26 , H01L23/5227 , H01L28/10 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a resonator made up of three sections (i.e., first, second and third sections) of a semiconductor layer. The second section has an end abutting the first section, a middle portion (i.e., an inductor portion) coiled around the first section and another end abutting the third section. The first and third sections exhibit a higher capacitance to the wafer substrate than the second section. Also disclosed are a process control system and method that incorporate one or more of these resonators. Specifically, during processing by a processing tool, wireless interrogation unit(s) detect the frequency response of resonator(s) in response to an applied stimulus. The detected frequency response is measured and used as the basis for making real-time adjustments to input settings on the processing tool (e.g., as the basis for making real-time adjustments to the temperature setting(s) of an anneal chamber).
摘要翻译： 公开了由半导体层的三个部分（即第一，第二和第三部分）构成的谐振器。 第二部分具有邻接第一部分的端部，围绕第一部分卷绕的中间部分（即电感器部分），以及抵靠第三部分的另一端部。 与第二部分相比，第一和第三部分显示比晶片衬底更高的电容。 还公开了并入这些谐振器中的一个或多个的过程控制系统和方法。 具体地，在处理工具的处理期间，无线询问单元响应于所施加的刺激来检测谐振器的频率响应。 测量检测到的频率响应并将其用作对处理工具上的输入设置进行实时调整的基础（例如，作为对退火室的温度设置进行实时调整的基础）。
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公开(公告)号：US08232215B2
公开(公告)日：2012-07-31
申请号：US12622557
申请日：2009-11-20
IPC分类号： H01L21/302
CPC分类号： H01L21/31144
摘要： A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.
摘要翻译： 用于形成邻接多个均匀间隔的地形特征的多个可变线宽间隔物的方法在位于多个均匀间隔的地形特征之上的间隔物材料层上使用共形抗蚀剂层。 保形抗蚀剂层被差异地曝光和显影以提供在形成可变线宽间隔物时用作牺牲掩模的差分厚度抗蚀剂层。 用于形成均匀线宽间隔物的方法，其邻接狭窄间隔的地形特征和在相同基底上的宽间隔的地形特征，使用可变厚度间隔物材料层的掩蔽各向同性蚀刻，以提供更均匀的部分蚀刻的间隔物材料层，随后是未掩模的各向异性蚀刻 的部分蚀刻的间隔材料层。 用于形成均匀线宽间隔物的相关方法使用包括至少一个掩模处理步骤的两步各向异性蚀刻方法。
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公开(公告)号：US20120149200A1
公开(公告)日：2012-06-14
申请号：US12966432
申请日：2010-12-13
申请人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
发明人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L21/28035 , H01L21/76237 , H01L21/823425 , H01L21/823468 , H01L21/823481 , H01L29/78
摘要： A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.
摘要翻译： 一种形成电介质间隔物的方法，包括提供包括具有第一多个栅极结构的第一区域和具有第二多个栅极结构的第二区域和至少一种含氧化物的材料或含碳材料的衬底。 在第一区域上形成厚度小于存在于第二区域中的含氮化物层的厚度的含氮化物层。 在第一多个第二多个栅极结构上从氮化物含有层形成电介质间隔物。 所述至少一种含氧化物的材料或含碳材料加速了第二区域中的蚀刻，使得第一区域中的电介质间隔物的厚度基本上等于衬底的第二区域中的电介质间隔物的厚度。
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49.发明申请公开(公告)号：US20090021314A1
公开(公告)日：2009-01-22
申请号：US12128654
申请日：2008-05-29
CPC分类号： H03L1/022 , H03L1/04 , H03L7/0995
摘要： A design structure for an apparatus for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs, is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.
摘要翻译： 一种用于利用设置在集成电路器件，芯片等上的单组一个或多个热传感器（例如热二极管）的设备的设计结构，以控制集成电路器件，相关联的冷却系统和 提供高频PLL。 通过利用单组热传感器来提供多种功能，例如控制集成电路器件，冷却系统和PLL的操作，通过组合电路功能降低硅的不动产使用。 此外，通过降低电路复杂度并增加PLL对于温度的鲁棒性，可以提高集成电路器件的产量。 此外，通过补偿温度来提高PLL电路的工作范围。
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公开(公告)号：US06510394B2
公开(公告)日：2003-01-21
申请号：US09776312
申请日：2001-02-02
IPC分类号： G01R2700
CPC分类号： H02M3/07
摘要： A system and method is provided for monitoring a voltage level of a charge pump device. The system and method employ a first charging device that is coupled to an output of a charge pump through a switching system. The first charging device is then decoupled from the output of the charge pump device and coupled to a second charging device. The charge on the first charging device is then redistributed between the first charging device and the second charging device. The output of the second charging device is a reduced voltage (e.g., below 5 volts) based on the ratio of the charge distribution between the first and second charging devices. The output of the second charging device can then be compared to a reference voltage to determine if the voltage of the charge pump device is at an adequate voltage level.
摘要翻译： 提供了一种用于监测电荷泵装置的电压电平的系统和方法。 该系统和方法采用通过交换系统耦合到电荷泵的输出的第一充电装置。 然后，第一充电装置与电荷泵装置的输出端分离并耦合到第二充电装置。 然后，第一充电装置的充电在第一充电装置和第二充电装置之间重新分配。 基于第一和第二充电装置之间的电荷分布的比例，第二充电装置的输出是降低的电压（例如，低于5伏特）。 然后可以将第二充电装置的输出与参考电压进行比较，以确定电荷泵装置的电压是否处于足够的电压水平。
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