公开(公告)号：US09373542B2

公开(公告)日：2016-06-21

申请号：US14081749

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Xiuyu Cai ,  Hoon Kim

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76855 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions.

Abstract translation: 提供具有改进的接触结构的集成电路和用于制造具有改进的接触结构的集成电路的方法。 在示例性实施例中，用于制造集成电路的方法包括在半导体衬底内和/或半导体衬底上提供器件。 此外，该方法包括形成与该装置电接触的接触结构。 接触结构包括覆盖该装置的硅酸盐阻挡部分，覆盖该装置并且位于硅酸盐阻挡部分之间的阻挡金属以及覆盖该阻挡金属并位于硅酸盐阻挡部分之间的填充金属。

公开(公告)号：US09343406B2

公开(公告)日：2016-05-17

申请号：US14550531

申请日：2014-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Kunaljeet Tanwar

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include forming a cavity in a SiO-based ILD; conformally forming a doped TaN layer in the cavity and over the ILD; conformally forming a Ru layer on the doped TaN layer; depositing Cu over the Ru layer and filling the cavity; planarizing the Cu, Ru layer, and doped TaN layer down to an upper surface of the ILD; forming a dielectric cap over the Cu, Ru layer, and doped TaN layer; and filling spaces formed between the dielectric cap and the doped TaN layer.

Abstract translation: 提供了形成与Cu互连结构的Ru层相邻的掺杂TaN Cu势垒的方法和所得到的器件。 实施例包括在SiO基ILD中形成空腔; 在空腔中并在ILD上保形地形成掺杂的TaN层; 在掺杂的TaN层上保形地形成Ru层; 在Ru层上沉积Cu并填充空腔; 将Cu，Ru层和掺杂的TaN层平坦化到ILD的上表面; 在Cu，Ru层和掺杂的TaN层上形成电介质盖; 以及形成在电介质盖和掺杂的TaN层之间的填充空间。

公开(公告)号：US09275874B2

公开(公告)日：2016-03-01

申请号：US14015640

申请日：2013-08-30

Applicant: GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

Inventor： Kunaljeet Tanwar ,  Xunyuan Zhang ,  Donald Canaperi ,  Raghuveer Patlolla

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/321

CPC classification number: H01L21/3212 ,  H01L21/32115 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/7688 ,  H01L21/76883

Abstract: Methods for fabricating integrated circuits using chemical mechanical planarization (CMP) for recessing metal are provided. In an embodiment, a method for fabricating an integrated circuit includes filling a trench with a metal and forming an overburden portion of the metal outside of the trench. The method further includes performing a planarization process with an etching slurry to remove the overburden portion of the metal and to recess the metal within the trench.

Abstract translation: 提供了使用用于凹陷金属的化学机械平面化（CMP）的集成电路的方法。 在一个实施例中，用于制造集成电路的方法包括用金属填充沟槽并在沟槽外部形成金属的覆盖层部分。 该方法还包括用蚀刻浆料进行平坦化处理以去除金属的覆盖层部分并使沟槽内的金属凹陷。

公开(公告)号：US20160049370A1

公开(公告)日：2016-02-18

申请号：US14457370

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal Kamineni ,  Xiuyu Cai ,  Xunyuan Zhang

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/285 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed herein includes, among other things, forming at least one layer of insulating material above a semiconductor layer, performing at least one contact opening etching process to form a contact opening in the at least one layer of insulating material that exposes a portion of the semiconductor layer, selectively depositing a metal-oxide insulating material through the contact opening on the exposed surface of the semiconductor layer, and forming a conductive contact in the contact opening that contacts the metal-oxide insulating material.

Abstract translation: 本文公开的一种方法包括在半导体层之上形成至少一层绝缘材料，执行至少一个接触开口蚀刻工艺，以在所述至少一层绝缘材料中形成接触开口，该绝缘材料层暴露一部分 半导体层，通过半导体层的暴露表面上的接触开口选择性地沉积金属氧化物绝缘材料，并且在与金属氧化物绝缘材料接触的接触开口中形成导电接触。

公开(公告)号：US09209135B2

公开(公告)日：2015-12-08

申请号：US14227807

申请日：2014-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Hoon Kim ,  Vivian W. Ryan

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a recess defined in a dielectric layer, the recess having an upper sidewall portion extending to an upper corner of the recess and a lower sidewall portion below the upper sidewall portion. An interconnect structure is positioned in the recess. The interconnect structure includes a continuous liner layer having upper and lower layer portions positioned laterally adjacent to the upper and lower sidewall portions, respectively. The upper layer portion includes an alloy of a first transition metal and a second transition metal and the lower layer portion includes the second transition metal but not the first transition metal. The interconnect structure also includes a fill material substantially filling the recess, wherein the second transition metal has a higher wettability for the fill material than the alloy.

Abstract translation: 半导体器件包括限定在电介质层中的凹部，凹部具有延伸到凹部的上角部的上侧壁部分和在上侧壁部分下方的下侧壁部分。 互连结构定位在凹槽中。 互连结构包括连续的衬垫层，其具有分别位于上下侧壁部分的横向相邻的上层和下层部分。 上层部分包括第一过渡金属和第二过渡金属的合金，下层部分包括第二过渡金属，但不包括第一过渡金属。 互连结构还包括基本上填充凹部的填充材料，其中第二过渡金属对于填充材料具有比合金更高的润湿性。

公开(公告)号：US09190486B2

公开(公告)日：2015-11-17

申请号：US13682331

申请日：2012-11-20

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Xunyuan Zhang

IPC: H01L21/76 ,  H01L29/66 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成牺牲栅极结构。 在牺牲栅极结构周围形成间隔物，并且在间隔物和半导体衬底上沉积电介质材料。 该方法包括选择性地蚀刻间隔物以在牺牲栅极结构和电介质材料之间形成沟槽。 沟槽由沟槽表面限定，在该沟槽表面上沉积替代间隔物材料。 该方法合并替换间隔物材料的上部区域以在替换间隔物材料内包围空隙。

公开(公告)号：US09190260B1

公开(公告)日：2015-11-17

申请号：US14540504

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Seowoo Nam ,  Hyun-Jin Cho

IPC: H01L43/12 ,  H01L21/02 ,  H01L27/22

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L21/02 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

Abstract translation: 提供了不使用光刻掩模形成自对准MTJ的方法和所得到的器件。 实施例包括在金属层上形成第一电极，金属层凹入低k电介质层中; 在第一电极上形成MTJ层; 在MTJ层上形成第二电极; 将所述第二电极，所述MTJ层和所述第一电极的部分去除到所述低k电介质层; 在所述第二电极和所述低k电介质层上形成氮化硅基层; 并将氮化硅基层平坦化到第二电极。

公开(公告)号：US20150325622A1

公开(公告)日：2015-11-12

申请号：US14272916

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Sean Xuan Lin ,  Kunaljeet Tanwar

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Integrated circuits with magnetic tunnel junction (MTJ) structures and methods for fabricating integrated circuits with MTJ structures are provided. An exemplary method for fabricating an integrated circuit includes forming a first conductive line in electrical connection with an underlying semiconductor device. The method exposes a surface of the first conductive line. Further, the method selectively deposits a conductive material on the surface of the first conductive line to form an electrode contact. The method includes forming a MTJ structure over the electrode contact.

Abstract translation: 提供了具有磁隧道结（MTJ）结构的集成电路和用于制造具有MTJ结构的集成电路的方法。 用于制造集成电路的示例性方法包括形成与下面的半导体器件电连接的第一导线。 该方法暴露第一导线的表面。 此外，该方法选择性地将导电材料沉积在第一导电线的表面上以形成电极接触。 该方法包括在电极接触件上形成MTJ结构。

公开(公告)号：US09159610B2

公开(公告)日：2015-10-13

申请号：US14061319

申请日：2013-10-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Moosung Chae ,  Larry Zhao

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76858 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed.

Abstract translation: 一种用于制造集成电路的方法包括提供覆盖半导体衬底的导电材料和覆盖导电材料的电介质材料，其中开口暴露导电材料的表面和电介质材料的侧壁，并选择性地沉积第一层 导电材料的表面上的阻挡材料，其中电介质材料的侧壁保持暴露，第一阻挡材料使得如果在退火过程中退火，则第一阻挡材料将扩散到导电材料中。 该方法还包括修改暴露表面上的第一阻挡材料以形成第二阻挡材料，第二阻挡材料使得在退火过程期间，第二阻挡材料不会扩散到导电材料中并沉积第二阻挡层 沿着开口的侧壁的第一阻挡材料。 此外，该方法包括退火半导体衬底。 还公开了根据前述方法制造的集成电路。

公开(公告)号：US09076846B2

公开(公告)日：2015-07-07

申请号：US14071070

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Errol Todd Ryan ,  Kunaljeet Tanwar ,  Xunyuan Zhang

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76883

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first exposed surface including an elemental metal material and a second exposed surface including a barrier material. The elemental metal material has a first etch rate when exposed to a wet etchant and the barrier material has a second etch rate when exposed to the wet etchant. Further, the method includes modifying the first exposed surface to form a modified first exposed surface so as to reduce the first etch rate when exposed to the wet etchant and applying the wet etchant simultaneously to the modified first exposed surface and to the second exposed surface.

Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有包括元素金属材料的第一暴露表面和包括阻挡材料的第二暴露表面的半导体衬底。 当暴露于湿蚀刻剂时，元素金属材料具有第一蚀刻速率，并且当暴露于湿蚀刻剂时，阻挡材料具有第二蚀刻速率。 此外，该方法包括修改第一暴露表面以形成修改的第一暴露表面，以便当暴露于湿蚀刻剂时降低第一蚀刻速率，并将湿蚀刻剂同时施加到经修改的第一暴露表面和第二暴露表面。