公开(公告)号：US11721719B2

公开(公告)日：2023-08-08

申请号：US17074891

申请日：2020-10-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L21/763 ,  H01L29/165

CPC classification number: H01L29/0642 ,  H01L21/763 ,  H01L29/0826 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US11664470B2

公开(公告)日：2023-05-30

申请号：US17863922

申请日：2022-07-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Rajendran Krishnasamy ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Ramsey Hazbun

IPC: H01L31/0352 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/103 ,  H01L31/028

CPC classification number: H01L31/035281 ,  H01L31/028 ,  H01L31/02327 ,  H01L31/103 ,  H01L31/1808

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.

公开(公告)号：US11545577B2

公开(公告)日：2023-01-03

申请号：US17114554

申请日：2020-12-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak

IPC: H01L29/786 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/04

Abstract: Disclosed is a structure including a semiconductor layer with a device area and, within the device area, a monocrystalline portion and polycrystalline portion(s) that extend through the monocrystalline portion. The structure includes an active device including a device component, which is in device area and which includes polycrystalline portion(s). For example, the device can be a field effect transistor (FET) (e.g., a simple FET or a multi-finger FET for a low noise amplifier or RF switch) with at least one source/drain region, which is in the device area and which includes at least one polycrystalline portion that extends through the monocrystalline portion. The embodiments can vary with regard to the type of structure (e.g., bulk or SOI), with regard to the type of device therein, and also with regard to the number, size, shape, location, orientation, etc. of the polycrystalline portion(s). Also disclosed is a method for forming the structure.

公开(公告)号：US11469178B2

公开(公告)日：2022-10-11

申请号：US17126921

申请日：2020-12-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  John J. Pekarik ,  Vibhor Jain

IPC: H01L23/525 ,  H01L27/12 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a metal-free fuse structure and methods of manufacture. The structure includes: a first metal-free fuse structure comprising a top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material including end portions with a first electrical resistance and a fuse portion of a second, higher electrical resistance electrically connected to the end portions; and a second metal-free fuse structure comprising the top semiconductor material of semiconductor-on-insulator (SOI) technologies, the top semiconductor material of the second metal-free fuse structure including at least a fuse portion of a lower electrical resistance than the second, higher electrical resistance.

公开(公告)号：US11437522B2

公开(公告)日：2022-09-06

申请号：US16890063

申请日：2020-06-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Mark Levy ,  Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/786 ,  H01L21/763 ,  H01L29/06 ,  H01L29/423

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material.

公开(公告)号：US11411081B2

公开(公告)日：2022-08-09

申请号：US16855236

申请日：2020-04-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/78

Abstract: The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure.

公开(公告)号：US20210391425A1

公开(公告)日：2021-12-16

申请号：US16899086

申请日：2020-06-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Henry Aldridge ,  John J. Ellis-Monaghan ,  Michel J. Abou-Khalil

IPC: H01L29/10 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is formed over a channel region of a substrate. A first source/drain region is positioned in the substrate adjacent to a first sidewall of the gate structure, a second source/drain region is positioned in the substrate adjacent to a second sidewall of the gate structure, and an extension region is positioned in the substrate. The extension region includes first and second sections that each overlap with the first source/drain region. The first and second sections of the extension region are spaced apart along a longitudinal axis of the gate structure. A portion of the channel region is positioned along the longitudinal axis of the gate structure between the first and second sections of the extension region.

公开(公告)号：US11152520B1

公开(公告)日：2021-10-19

申请号：US16868773

申请日：2020-05-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark D. Levy ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L31/0232 ,  H01L27/144 ,  H01L31/18 ,  H01L31/105 ,  H01L31/028

Abstract: A photodetector includes a photodetecting region in a semiconductor substrate, and a reflector extending at least partially along a sidewall of the photodetecting region in the semiconductor substrate. The reflector includes an air gap defined in the semiconductor substrate. The reflector allows use of thinner germanium for the photodetecting region. The air gap may have a variety of internal features to direct electromagnetic radiation towards the photodetecting region.

公开(公告)号：US11121097B1

公开(公告)日：2021-09-14

申请号：US16881736

申请日：2020-05-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Sebastian T. Ventrone ,  Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Ajay Raman

IPC: H01L23/00 ,  H01L23/48

Abstract: The present disclosure relates to a metal layer for an active x-ray attack prevention device for securing integrated circuits. In particular, the present disclosure relates to a structure including a semiconductor material, one or more devices on a front side of the semiconductor material, a backside patterned metal layer under the one or more devices, located and structured to protect the one or more devices from an active intrusion, and at least one contact providing an electrical connection through the semiconductor material to a front side of the backside patterned metal layer. The backside patterned metal layer is between a wafer and one of the semiconductor material and an insulator layer.

公开(公告)号：US20210272812A1

公开(公告)日：2021-09-02

申请号：US16806383

申请日：2020-03-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Anthony K. Stamper ,  Michel J. Abou-Khalil ,  John J. Ellis-Monaghan ,  Bojidha Babu

IPC: H01L21/265 ,  H01L29/04 ,  H01L21/324 ,  H01L21/762

Abstract: Structures including electrical isolation and methods of forming a structure including electrical isolation. A first polycrystalline layer is located in a substrate, and a second polycrystalline layer is positioned between the first polycrystalline layer and a top surface of the substrate. The substrate includes a first portion of the single-crystal semiconductor material that is positioned between the second polycrystalline layer and the top surface of the substrate. The substrate includes a second portion of the single-crystal semiconductor material that is positioned between the first polycrystalline layer and the second polycrystalline layer. The first polycrystalline layer has a thickness. The second polycrystalline layer has a portion with a thickness that is greater than the thickness of the first polycrystalline layer.