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公开(公告)号：US10236063B2
公开(公告)日：2019-03-19
申请号：US15986531
申请日：2018-05-22
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Boon Bing Ng , Thida Ma Win , Ning Ge , Jose Jehrome Rando
Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.
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公开(公告)号：US10173420B2
公开(公告)日：2019-01-08
申请号：US15558618
申请日：2015-07-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Wai Mun Wong , Leong Yap Chia , Ning Ge
Abstract: The present subject matter relates to a printhead assembly comprising a plurality of print nozzles in a nozzle array. Each of the plurality of print nozzles is coupled to a printhead firing resistor, the printhead firing resistor being individually addressable. A print control circuit is to actuate the printhead firing resistor. In accordance with one example implementation of the present subject matter, the print control circuit comprises pull-down resistors made of Tantalum-Aluminum (Ta—Al).
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公开(公告)号：US10162263B2
公开(公告)日：2018-12-25
申请号：US15547105
申请日：2015-04-27
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Ning Ge , Zhiyong Li , Jianhua Yang , R. Stanley Williams
IPC: H01L27/00 , H01L45/00 , G03F7/16 , G11C13/00 , G11C19/28 , B41J2/045 , B41J2/14 , H01L27/108 , H01L49/02 , H01L27/24
Abstract: An integrated circuit may include a substrate with a plurality of transistors formed in the substrate. The plurality of transistors may be coupled to a first metal layer formed over the plurality of transistors. A plurality of high dielectric nanometer capacitors may be formed of memristor switch material between the first metal layer and a second metal layer formed over the plurality of high dielectric capacitors. The plurality of high dielectric capacitors may operate as memory storage cells in dynamic logic.
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公开(公告)号：US20180275065A1
公开(公告)日：2018-09-27
申请号：US15764240
申请日：2016-01-29
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Anita Rogacs , Viktor Shkolnikov , Ning Ge
CPC classification number: G01N21/658 , G01J3/0202 , G01J3/0208 , G01J3/021 , G01J3/0237 , G01J3/0256 , G01J3/0291 , G01J3/44 , G01N21/648
Abstract: An analyte detection system includes an analyte detection package to be presented to a reading device, and a focus mechanism to adjust a focal point of the analyte detection package relative to the reading device, with the analyte detection package including a surface-enhanced luminescence analyte stage, the reading device including optics to receive scattered radiation emitted luminescence from the analyte stage, and the focus mechanism to adjust the focal point relative to the optics.
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公开(公告)号：US10082414B2
公开(公告)日：2018-09-25
申请号：US15423266
申请日：2017-02-02
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Ning Ge , Trudy Benjamin , Teck-Khim Neo , Joseph M. Torgerson , Neel Banerjee , George H. Corrigan, III
CPC classification number: G01F23/263 , B41J2/14153 , B41J2/175 , B41J2/17566 , B41J2002/17579
Abstract: In some examples, an ink level sensor includes a sense capacitor between a first node and ground, a first switch to couple a first voltage to the first node and charge the sense capacitor, a second switch to couple the first node with a second node and share the charge between the sense capacitor and a reference capacitor, causing a second voltage at the second node, and a transistor having a drain, a gate coupled to the second node, and a source coupled to ground, the transistor to provide a drain to source resistance in proportion to the second voltage.
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Patent Agency Ranking
公开(公告)号：US10081178B2
公开(公告)日：2018-09-25
申请号：US15877971
申请日：2018-01-23
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Ning Ge , Leong Yap Chia , Wai Mun Wong
CPC classification number: B41J2/04541 , B41J2/04543 , B41J2/0458 , B41J2/04581 , B41J2/04586 , G11C16/08 , G11C16/32
Abstract: Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a plurality of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the plurality of cells. A column shift register is coupled to the column select ports of the plurality of cells, the column shift register having a register location for each column of the plurality of cells and having an input to receive a first input signal. A row shift register is coupled to row select ports of the plurality of cells, the row shift register having a register location for each row of the plurality of cells and having an input to receive a second input signal.
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公开(公告)号：US20180268905A1
公开(公告)日：2018-09-20
申请号：US15986531
申请日：2018-05-22
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Boon Bing Ng , Thida Ma Win , Ning Ge , Jose Jehrome Rando
Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.
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公开(公告)号：US10076904B2
公开(公告)日：2018-09-18
申请号：US15637272
申请日：2017-06-29
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Jianhua Yang , Ning Ge , Zhiyong Li
Abstract: In some examples, an integrated circuit device includes a substrate, a memristor over the substrate and comprising a first metal layer as a first electrode, a second metal layer as a second electrode, and a switching oxide layer between the first and second metal layers, and a thermal resistor layer over the substrate.
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公开(公告)号：US09776419B2
公开(公告)日：2017-10-03
申请号：US15118393
申请日：2014-03-07
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Ning Ge , Patrick Leonard , Adam L. Ghozeil
IPC: B41J2/175
CPC classification number: B41J2/17566 , B41J2/04541 , B41J2/04566 , B41J2/04571 , B41J2/14072 , B41J2/1412 , B41J2/14129 , B41J2/14153 , B41J2002/14354 , B41J2202/18
Abstract: An example provides a fluid ejection device including a fluid feed slot, a fluid chamber between a nozzle layer and a passivation layer, and a printhead-integrated sensor to sense a property of a fluid in the fluid chamber. The sensor may include a ground electrode exposed to the fluid chamber through a via in the passivation layer.
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公开(公告)号：US09751320B2
公开(公告)日：2017-09-05
申请号：US15024339
申请日：2013-09-27
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Ning Ge
CPC classification number: B41J2/17566 , B41J2/0451 , B41J2/04565 , B41J2/0458 , B41J2/04581 , B41J2/14153 , G01F23/0061
Abstract: A printhead with a separate address generator for ink level sensors is described. In an example, a printhead includes drop ejectors fluidically coupled to nozzles, at least one nozzle address generator, nozzle decoders coupled to nozzle address generator(s) and the drop ejectors, ink level sensors each having a sensor circuit in a sensor chamber and a purging resistor circuit, a sensor address generator, and sensor decoders coupled to the sensor address generator and the purging resistor circuit in each of the ink level sensors.
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