公开(公告)号：US08951862B2

公开(公告)日：2015-02-10

申请号：US13347331

申请日：2012-01-10

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L21/336

CPC classification number: H01L27/11582 ,  H01L29/7926

Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.

Abstract translation: 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 诸如硅的导电线形成在堆叠的非易失性存储器结构之上。 字线沟槽分离出相邻的硅线。 由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。 字线是在字线沟中制作的。

公开(公告)号：US08861273B2

公开(公告)日：2014-10-14

申请号：US12427587

申请日：2009-04-21

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51

CPC classification number: H01L21/28282 ,  G11C16/0433 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

Abstract: A 2T cell NOR architecture based on the use of BE-SONOS for embedded memory includes memory cells having respective access transistors having access gates and memory transistors having memory gates arranged in series between the corresponding bit lines and one of the plural reference lines. A memory transistor in a memory cell comprises a semiconductor body including a channel having a channel surface and a charge storing dielectric stack between the memory gate and the channel surface. The dielectric stack comprises a bandgap engineered, tunneling dielectric layer contacting one of the gate (for gate injection tunneling) and the channel surface (for channel injection tunneling). The dielectric stack of the memory cell also includes a charge trapping dielectric layer on the tunneling dielectric layer and a blocking dielectric layer.

Abstract translation: 基于对嵌入式存储器使用BE-SONOS的2T单元NOR架构包括具有存取晶体管的存储单元，存储晶体管具有存取栅极和存储晶体管，存储晶体管具有串联布置在相应的位线和多条参考线之一中的存储栅极。 存储单元中的存储晶体管包括半导体本体，其包括具有沟道表面的沟道和在存储器栅极和沟道表面之间的电荷存储电介质叠层。 电介质堆叠包括接触栅极（用于栅极注入隧道）和沟道表面之一（用于沟道注入隧道）的带隙工程化的隧道电介质层。 存储单元的电介质叠层还包括在隧道介电层上的电荷捕获电介质层和阻挡电介质层。

公开(公告)号：US08860124B2

公开(公告)日：2014-10-14

申请号：US12553758

申请日：2009-09-03

Applicant: Hang-Ting Lue ,  Yi-Hsuan Hsiao

Inventor： Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC: H01L29/66 ,  H01L27/115 ,  H01L29/51 ,  H01L29/792 ,  G11C16/04

CPC classification number: H01L29/792 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/513

Abstract: A memory device includes a plurality of semiconductor lines, such as body-tied fins, on a substrate. The lines including buried-channel regions doped for depletion mode operation. A storage structure lies on the plurality of lines, including tunnel insulating layer on the channel regions of the fins, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer. A plurality of word lines overlie the storage structure and cross over the channel regions of the semiconductor lines, whereby memory cells lie at cross-points of the word lines and the semiconductor lines.

Abstract translation: 存储器件在衬底上包括多个半导体线，例如体结翅片。 这些线包括掺杂用于耗尽模式操作的掩埋沟道区。 存储结构位于多条线上，包括鳍状物的沟道区上的隧道绝缘层，隧道绝缘层上的电荷存储层，以及电荷存储层上的阻挡绝缘层。 多个字线覆盖在存储结构上并与半导体线的沟道区交叉，由此存储单元位于字线和半导体线的交叉点。

公开(公告)号：US08846549B2

公开(公告)日：2014-09-30

申请号：US11235786

申请日：2005-09-27

Applicant: Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

Inventor： Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC: H01L21/31 ,  G11C16/04 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/28282 ,  G11C16/0466 ,  H01L29/513

Abstract: A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19 cm−3 and an interface trap density of up to 5E11 cm−2 eV−1. The three-layer structure may be a charge-trapping structure for the memory device, and the memory device may further include a gate over the structure and source and drain regions in the substrate.

Abstract translation: 半导体衬底上的非易失性存储器件可以包括衬底上的底部氧化物层，底部氧化物层上的中间氮化硅层和中间层上的顶部氧化物层。 底部氧化物层可以具有高达5E19cm-3的氢浓度和高达5E11cm-2eV-1的界面陷阱密度。 三层结构可以是用于存储器件的电荷捕获结构，并且存储器件还可以包括在结构上的栅极和衬底中的源极和漏极区域。

公开(公告)号：US08643078B2

公开(公告)日：2014-02-04

申请号：US13443417

申请日：2012-04-10

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

IPC: H01L29/788

CPC classification number: H01L23/3192 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基极，层叠结构和掺杂层。 堆叠结构形成在基底上，其中堆叠结构包括多个导电条和多个绝缘条，其中一个导电条位于相邻的两个绝缘条之间，该堆叠结构具有第一侧壁和 第一侧壁的长边缘沿着通道方向延伸。 掺杂层形成在第一侧壁中，其中通过施加到第一侧壁上的离子注入形成掺杂层，并且在离子注入的注入方向和第一侧壁之间包含锐角。

公开(公告)号：US20130334575A1

公开(公告)日：2013-12-19

申请号：US13527259

申请日：2012-06-19

Applicant: Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

IPC: H01L27/10 ,  H01L21/768

CPC classification number: H01L27/11578 ,  H01L27/11565

Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.

Abstract translation: 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。 通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。 在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

公开(公告)号：US20130214340A1

公开(公告)日：2013-08-22

申请号：US13401634

申请日：2012-02-21

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L29/68 ,  H01L21/283

CPC classification number: H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基板，第一堆叠结构和第一导电层。 第一堆叠结构形成在基板上，并且包括导电结构和绝缘结构，并且导电结构邻近于绝缘结构设置。 第一导电层形成在基板上并且包围第一层叠结构的两个侧壁和顶部的一部分，用于暴露第一堆叠结构的一部分。

公开(公告)号：US08503213B2

公开(公告)日：2013-08-06

申请号：US13078311

申请日：2011-04-01

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: G11C5/06

CPC classification number: H01L27/11578 ,  G11C13/0002 ,  G11C16/0483 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/11573

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的导电材料条带形式的脊形叠层，排列成可通过解码电路耦合到读出放大器的位线。 二极管与字符串的公共源选择端的字符串选择连接到位线。 导电材料条具有在脊形叠层的侧面上的侧表面。 可以耦合到行解码器的多个字线在多个脊形叠层上正交延伸。 存储元件位于堆叠上的半导体条的侧表面和字线之间的交叉点处的界面区域的多层阵列中。

公开(公告)号：US08432719B2

公开(公告)日：2013-04-30

申请号：US13008384

申请日：2011-01-18

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C11/00

CPC classification number: H01L27/11556 ,  G11C8/16 ,  G11C16/0416 ,  H01L27/11524

Abstract: A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, wherein one set of channels is sandwiched between the adjacent sets of bit lines and source lines.

Abstract translation: 3D堆叠的AND型闪速存储器结构包括以三维阵列布置的多个存储单元的水平面，并且每个水平面包括交替布置的多个字线和几个电荷俘获多层，并且相邻的字线与每个 其他每个电荷捕获多层介于其间; 交替布置并垂直于水平面布置的多组位线和源极线; 以及交替布置并且垂直于水平面布置的多组绝缘柱和一组绝缘柱，其中一组通道夹在相邻的位线组和源极线之间。

公开(公告)号：US08426294B2

公开(公告)日：2013-04-23

申请号：US13476964

申请日：2012-05-21

Applicant: Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

Inventor： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

IPC: H01L29/76

CPC classification number: G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

Abstract translation: 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。