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93 条记录 (耗时 0.034 秒)

    Bias circuit for a MOS device
    44.
    发明授权
    Bias circuit for a MOS device 有权
    用于MOS器件的偏置电路

    公开(公告)号：US07936208B2

    公开(公告)日：2011-05-03

    申请号：US12184148

    申请日：2008-07-31

    申请人： Steven Mark Clements ,  Hayden C. Cranford, Jr. ,  Amar Chandra Mahadeo Dwarka ,  John Farley Ewen

    发明人： Steven Mark Clements ,  Hayden C. Cranford, Jr. ,  Amar Chandra Mahadeo Dwarka ,  John Farley Ewen

    IPC分类号： G05F3/02

    CPC分类号： G05F3/205

    摘要： A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit includes utilizing a current mirror circuit coupled to the at least one diode connected circuit to generate a bias voltage for the body of the semiconductor device from the voltage. The bias voltage allows for compensation for the process, voltage and temperature variations.

    摘要翻译： 公开了一种用于向MOS器件提供偏置电压的方法和电路。 该方法和电路包括利用至少一个二极管连接的电路来提供跟踪半导体器件的工艺，电压和温度变化的电压。 所述方法和电路包括利用耦合到所述至少一个二极管连接的电路的电流镜电路，以从所述电压产生所述半导体器件的主体的偏置电压。 偏置电压允许对过程，电压和温度变化进行补偿。

    Systems and arrangements for clock and data recovery in communications
    45.
    发明授权
    Systems and arrangements for clock and data recovery in communications 有权
    通信中时钟和数据恢复的系统和安排

    公开(公告)号：US07916820B2

    公开(公告)日：2011-03-29

    申请号：US11608962

    申请日：2006-12-11

    申请人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

    发明人： Hayden C. Cranford, Jr. ,  Daniel J. Friedman ,  Mounir Meghelli ,  Thomas H. Toifl

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0004 ,  H04L7/0334

    摘要： A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the CDR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.

    摘要翻译： 公开了一种双模式时钟和数据恢复（CDR）系统。 快速锁定，过采样CDR采集模块可以开始该过程，以在启动数据采集条件下快速创建数据采集时钟信号。 当从输入数据流中至少提取一些数据时，CDR系统可以指示这种稳定性，并切换到接受来自低功率CDR维护模块的控制。 低功率CDR维护模块可以微调并保持数据采集信号的定时。 如果CDR维护模块控制下的数据锁定质量下降到足够的程度，高功率CDR采集模块可以重新启用并重新从低功率模块重新进行控制，直到锁定质量再次足够 要使用的低功耗模块。

    Structure for on-chip electromigration monitoring system
    46.
    发明授权
    Structure for on-chip electromigration monitoring system 有权
    片上电迁移监控系统结构

    公开(公告)号：US07840916B2

    公开(公告)日：2010-11-23

    申请号：US11985966

    申请日：2007-11-19

    申请人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

    发明人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Oleg Gluschenkov ,  James S. Mason ,  Michael A. Sorna ,  Chih-Chao Yang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G01R31/2858

    摘要： A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.

    摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构可以包括半导体芯片的装置，其可操作以检测半导体芯片的被监测元件的电阻的增加。 该设计结构可以包括例如可操作以输出具有不同值的多个参考电压的电阻分压器电路。 可以将半导体芯片中的多个比较器耦合以接收参考电压和表示所监视元件的电阻的监视电压。 每个比较器可以产生指示监视的电压是否超过参考电压的输出，使得可以精确地确定被监视元件的电阻值。

    System and circuit for constructing a synchronous signal diagram from asynchronously sampled data
    47.
    发明授权
    System and circuit for constructing a synchronous signal diagram from asynchronously sampled data 有权
    用于从异步采样数据构建同步信号图的系统和电路

    公开(公告)号：US07792649B2

    公开(公告)日：2010-09-07

    申请号：US12055317

    申请日：2008-03-26

    申请人： Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

    发明人： Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

    IPC分类号： G06F19/00

    CPC分类号： H04L1/205 ,  G01R31/31709

    摘要： A system and circuit for constructing a synchronous signal diagram from asynchronous sampled data provides a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase to find a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.

    摘要翻译： 用于从异步采样数据构建同步信号图的系统和电路为提供信号图提供了低成本和生产可集成技术。 数据信号被边缘检测和异步采样（或者时钟信号被锁存）。 将数据信号或第二信号与可设置的阈值电压进行比较并采样。 边缘和比较数据根据扫描时基折叠以找到最小抖动周期。 信号图边缘的交叉由折叠边缘数据的直方图的峰值确定。 对于每个阈值电压产生样本值与交叉位置位置之间的位移比率的直方图。 该技术在可设置的阈值电压范围内重复。 然后，相对于阈值电压，在直方图之间区分比率计数，从中填充信号图。

    CML delay cell with linear rail-to-rail tuning range and constant output swing
    49.
    发明授权
    CML delay cell with linear rail-to-rail tuning range and constant output swing 失效
    CML延迟单元具有线性轨至轨调谐范围和恒定输出摆幅

    公开(公告)号：US07541855B2

    公开(公告)日：2009-06-02

    申请号：US12124384

    申请日：2008-05-21

    申请人： Hayden C. Cranford, Jr. ,  Marcel A. Kossel ,  Thomas E. Morf

    发明人： Hayden C. Cranford, Jr. ,  Marcel A. Kossel ,  Thomas E. Morf

    IPC分类号： H03H11/26

    CPC分类号： H03K5/13 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00208

    摘要： A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I0, and a compensation circuit having switching point optimized inverters having a first plurality of transistors having a transconductance βpN and a second plurality of transistors having a transconductance βnN, wherein respective ratios of βnN/βpN determine an inverter switching point of respective switching point optimized inverters, the first and second plurality of transistors having gates coupled to the tuning voltage input of the CML delay cell, wherein the switching point optimized inverters are followed by weighted tail current sources M0N that supply additional currents to the current source I0 at a drain node of the third transistor.

    摘要翻译： 具有线性轨至轨调谐范围和恒定输出摆幅的电流模式逻辑（CML）延迟单元。 CML延迟单元可以包括在第一和第二晶体管上的调谐电压输入，有助于CML延迟单元负载，以及作为电流源I0在第三晶体管上输入的偏置电压，以及具有开关点优化的逆变器的补偿电路 具有跨导betapN的第一多个晶体管和具有跨导betanN的第二多个晶体管，其中，betanN / betapN的各自比例确定各个开关点优化的反相器的反相器切换点，第一和第二多个晶体管具有栅极耦合 到CML延迟单元的调谐电压输入，其中开关点优化的反相器之后是在第三晶体管的漏极节点向电流源I0提供附加电流的加权尾电流源M0N。