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    Semiconductor memory device comprising memory cells with floating gate electrode and method of production
    41.
    发明申请
    Semiconductor memory device comprising memory cells with floating gate electrode and method of production 有权
    半导体存储器件包括具有浮栅电极的存储单元和制造方法

    公开(公告)号：US20060038220A1

    公开(公告)日：2006-02-23

    申请号：US10921766

    申请日：2004-08-19

    申请人： Karl-Heinz Kusters ,  Josef Willer ,  Corvin Liaw

    发明人： Karl-Heinz Kusters ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L29/788

    CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/792

    摘要： Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.

    摘要翻译： 位于浅沟槽隔离物之间的半导体衬底的主表面处的半导体材料的晶体管本体具有圆形或弯曲的上表面。 浮栅电极布置在所述上​​表面之上并且通过隧道电介质与半导体材料电绝缘，所述隧道电介质具有贯穿所述曲率区域的主隧道区域具有基本上相同的微小厚度。 浮栅电极可以桥接晶体管本体，并被形成为形成字线一部分的控制栅电极的耦合电介质覆盖。

    Integrated circuit with Resistivity changing memory cells and methods of operating the same
    42.
    发明授权
    Integrated circuit with Resistivity changing memory cells and methods of operating the same 有权
    具有电阻率变化的存储单元的集成电路及其操作方法

    公开(公告)号：US07706201B2

    公开(公告)日：2010-04-27

    申请号：US11778549

    申请日：2007-07-16

    申请人： Corvin Liaw ,  Michael Angerbauer ,  Peter Schroegmeier

    发明人： Corvin Liaw ,  Michael Angerbauer ,  Peter Schroegmeier

    IPC分类号： G11C7/02

    CPC分类号： G11C13/00 ,  G11C5/02 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/79

    摘要： An integrated circuit includes a plurality of resistivity changing memory cells and at least one resistivity changing reference cell; a voltage comparator including a first and second input terminals; a signal line connected to the memory cells, the reference cell, and the second input terminal; and a switching element connecting the first input terminal to the second input terminal. A method of operating the integrated circuit includes closing the switching element; supplying a first voltage to the first input terminal via the signal line and the switching element; opening the switching element; supplying a second voltage to the second input terminal via the signal line; and comparing the first and second voltages using the voltage comparator, wherein the first voltage represents a memory state of a memory cell, and the second voltage is a reference voltage which represents a memory state of a reference cell, or vice versa.

    摘要翻译： 集成电路包括多个电阻率变化存储单元和至少一个电阻率变化参考单元; 电压比较器，包括第一和第二输入端子; 连接到存储器单元，参考单元和第二输入端子的信号线; 以及将第一输入端子连接到第二输入端子的开关元件。 一种操作集成电路的方法包括：关闭开关元件; 经由所述信号线和所述开关元件向所述第一输入端提供第一电压; 打开开关元件; 经由信号线向第二输入端提供第二电压; 以及使用所述电压比较器来比较所述第一和第二电压，其中所述第一电压表示存储器单元的存储状态，并且所述第二电压是表示参考单元的存储器状态的参考电压，反之亦然。

    Charge-trapping memory device and methods for operating and manufacturing the cell
    43.
    发明授权
    Charge-trapping memory device and methods for operating and manufacturing the cell 有权
    电荷捕获存储器件以及用于操作和制造电池的方法

    公开(公告)号：US07402490B2

    公开(公告)日：2008-07-22

    申请号：US11253939

    申请日：2005-10-19

    申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

    摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

    摘要翻译： 为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。 栅电极层被构造成形成具有侧壁的栅电极。 执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。 边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。 然后可以沉积电荷捕获层材料以填充空间。 然后在与栅电极相邻的半导体本体中形成源区和漏区。

    Integrated memory device and method for operating the same
    44.
    发明授权
    Integrated memory device and method for operating the same 有权
    集成存储器件及其操作方法

    公开(公告)号：US07280392B2

    公开(公告)日：2007-10-09

    申请号：US11339846

    申请日：2006-01-26

    申请人： Corvin Liaw ,  Josef Willer

    发明人： Corvin Liaw ,  Josef Willer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0011 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2213/77 ,  H01L27/101

    摘要： A memory device includes an array of memory cells that include a memory element having a non-reactive resistance whose magnitude is programmable to assume a high-resistance state or a low-resistance state. Sets of first and second lines provide access to the memory cells, wherein the memory element of each memory cell is coupled between one of the first lines and one of the second lines. A checking unit determines whether to invert data values to be stored in memory cells coupled to at least a section of respective ones of the first lines based on a number of memory cells that would be programmed in the high-resistance state or the low-resistance state as a result of the data values in order to reduce the number memory cells programmed in the low-resistance state and the resulting leakage current.

    摘要翻译： 存储器件包括存储器单元阵列，其包括具有非反应电阻的存储元件，其大小可编程为呈现高电阻状态或低电阻状态。 第一和第二行的集合提供对存储器单元的访问，其中每个存储器单元的存储元件耦合在第一行之一和第二行中的一个之间。 检查单元基于将以高电阻状态编程的存储器单元的数量或低电阻来确定是否反转要存储在耦合到第一行中的相应的第一行的至少一部分的存储器单元中的数据值 作为数据值的结果，为了减少在低电阻状态下编程的存储单元数量和所产生的漏电流。

    Resistive Memory Arrangement
    45.
    发明申请
    Resistive Memory Arrangement 有权
    电阻记忆布置

    公开(公告)号：US20070211515A1

    公开(公告)日：2007-09-13

    申请号：US11688556

    申请日：2007-03-20

    申请人： Corvin Liaw ,  Thomas Roehr ,  Michael Kund

    发明人： Corvin Liaw ,  Thomas Roehr ,  Michael Kund

    IPC分类号： G11C11/00

    CPC分类号： G11C13/003 ,  G11C13/0011 ,  G11C2213/78 ,  G11C2213/79

    摘要： Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

    摘要翻译： 提供了具有以行和列构成的单元阵列并且具有连接到用于驱动的​​驱动元件的电阻性存储单元的电阻式存储器装置。 每个驱动元件共同连接到形成存储单元的n个单元电阻器，单元电阻器是CBRAM电阻元件，特别是与CBRAM电阻元件实现的用于电阻存储器布置的写入，读取和擦除方法。

    Semiconductor memory device comprising memory cells with floating gate electrode and method of production
    46.
    发明授权
    Semiconductor memory device comprising memory cells with floating gate electrode and method of production 有权
    半导体存储器件包括具有浮栅电极的存储单元和制造方法

    公开(公告)号：US07250651B2

    公开(公告)日：2007-07-31

    申请号：US10921766

    申请日：2004-08-19

    申请人： Karl-Heinz Küsters ,  Josef Willer ,  Corvin Liaw

    发明人： Karl-Heinz Küsters ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062

    CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/792

    摘要： Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.

    摘要翻译： 位于浅沟槽隔离物之间的半导体衬底的主表面处的半导体材料的晶体管本体具有圆形或弯曲的上表面。 浮栅电极布置在所述上​​表面之上并且通过隧道电介质与半导体材料电绝缘，所述隧道电介质具有贯穿所述曲率区域的主隧道区域具有基本上相同的微小厚度。 浮栅电极可以桥接晶体管本体，并被形成为形成字线一部分的控制栅电极的耦合电介质覆盖。

    Charge-trapping memory device and methods for operating and manufacturing the cell
    48.
    发明申请
    Charge-trapping memory device and methods for operating and manufacturing the cell 有权
    电荷捕获存储器件以及用于操作和制造电池的方法

    公开(公告)号：US20060091448A1

    公开(公告)日：2006-05-04

    申请号：US11253939

    申请日：2005-10-19

    申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

    摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

    摘要翻译： 为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。 栅电极层被构造成形成具有侧壁的栅电极。 执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。 边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。 然后可以沉积电荷捕获层材料以填充空间。 然后在与栅电极相邻的半导体本体中形成源区和漏区。