公开(公告)号：US4018739A

公开(公告)日：1977-04-19

申请号：US607962

申请日：1975-08-26

申请人： Masahiro Okamoto ,  Morio Kimura ,  Teruo Shibuya ,  Shinji Yamamoto ,  Shinichi Hasegawa ,  Yutaka Terada ,  Teruho Adachi

发明人： Masahiro Okamoto ,  Morio Kimura ,  Teruo Shibuya ,  Shinji Yamamoto ,  Shinichi Hasegawa ,  Yutaka Terada ,  Teruho Adachi

IPC分类号： C08G18/54 ,  C08G2/28 ,  C08G2/30

CPC分类号： C08G18/542 ,  Y10T428/16

摘要： A tar-urethane composition comprising (1) an isocyanate-reactive tar obtained by reacting a tar produced as a by-product in the phenol synthesis via hydroperoxides with a formaldehyde in the presence of a basic catalyst and in the presence or absence of at least one phenol compound and (2) a polyisocyanate, which is useful as coating agents, materials for pavement, floor linings, sealing materials and the like.

摘要翻译： 焦油 - 聚氨酯组合物，其包含（1）异氰酸酯反应性焦油，其通过在碱性催化剂的存在下，通过氢过氧化物在苯酚合成中作为副产物生成的焦油与至少存在或不存在 一种酚化合物和（2）多异氰酸酯，其可用作涂层剂，路面材料，地板衬里，密封材料等。

公开(公告)号：US08811078B2

公开(公告)日：2014-08-19

申请号：US13493671

申请日：2012-06-11

申请人： Yutaka Terada ,  Masakazu Kurata

发明人： Yutaka Terada ,  Masakazu Kurata

IPC分类号： G11C16/10 ,  H01L27/112 ,  H01L27/115 ,  G11C16/04 ,  G11C16/06

CPC分类号： H01L27/112 ,  G11C16/0408 ,  G11C16/06 ,  H01L27/115 ,  H01L27/11519

摘要： In a semiconductor memory device in which each memory cell is constituted by one transistor, in a memory cell pattern, two adjacent bits form one diffusion pattern, two adjacent transistors share a source region, and two drain regions are separated from each other. A plurality of arrays in each of which at least a column of the diffusion patterns is disposed include bit lines, and the bit lines of the first array are independent of the bit lines of the second array. In an interface between the arrays, ends at one side of the bit lines of each of the arrays are located on an associated one of two drain regions which are separated from each other with the source region which is shared on one diffusion pattern sandwiched therebetween. This configuration can provide a sufficient bit-line separation width, and reduce the area.

摘要翻译： 在其中每个存储单元由一个晶体管构成的半导体存储器件中，在存储单元图形中，两个相邻位形成一个扩散图案，两个相邻的晶体管共享源极区域，并且两个漏极区域彼此分离。 其中布置有至少一列扩散图案的多个阵列包括位线，并且第一阵列的位线与第二阵列的位线无关。 在阵列之间的接口中，每个阵列的位线的一侧的端部位于两个漏极区域中的相关联的一个上，这两个漏极区域彼此分离，其中源区域在夹在其间的一个扩散图案上共享。 这种配置可以提供足够的位线分隔宽度，并减少面积。

公开(公告)号：US20090180306A1

公开(公告)日：2009-07-16

申请号：US12243299

申请日：2008-10-01

申请人： Yutaka Terada ,  Yasuhiro Agata ,  Wataru Abe ,  Masakazu Kurata ,  Kenji Misumi

发明人： Yutaka Terada ,  Yasuhiro Agata ,  Wataru Abe ,  Masakazu Kurata ,  Kenji Misumi

IPC分类号： G11C5/06

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  H01L27/0207 ,  H01L27/112 ,  H01L27/11253

摘要： A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

摘要翻译： 分割存储器阵列的末端列上的电路由具有与存储单元晶体管相同形状的块选择晶体管形成。 由于主位线和子位线之间的连接部分的图形与存储单元的形状相同，所以可以实现图案均匀性，并且不需要使用存储器阵列虚拟图案 。

公开(公告)号：US20080253171A1

公开(公告)日：2008-10-16

申请号：US12039585

申请日：2008-02-28

申请人： Yutaka Terada ,  Satoshi Ishikura ,  Yoshinobu Yamagami ,  Toshio Terano

发明人： Yutaka Terada ,  Satoshi Ishikura ,  Yoshinobu Yamagami ,  Toshio Terano

IPC分类号： G11C11/00

CPC分类号： G11C29/50 ,  G11C11/41

摘要： A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.

摘要翻译： 半导体集成电路包括：包括多个SRAM存储单元的存储单元阵列; 包括并联连接的多个晶体管电路的特性测量电路; 和第一个终端。 多个晶体管电路各自包括以与包括在SRAM存储单元之一中的晶体管中的一个相同的方式配置的第一晶体管。 第一晶体管被连接以便根据提供给第一晶体管的栅极的电压来控制第一端子和参考电位的节点之间的电流。

公开(公告)号：US07149267B2

公开(公告)日：2006-12-12

申请号：US10995124

申请日：2004-11-24

申请人： Yutaka Terada ,  Takefumi Yoshikawa

发明人： Yutaka Terada ,  Takefumi Yoshikawa

IPC分类号： H04L7/00

CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/22

摘要： An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on which the data signal is intended to be latched. Based on the results of the comparison, the first and second delay circuits delay the clock signal for respectively predetermined amounts of time. If the data signal is logically high, then the selector selects a delayed clock signal supplied from the first delay circuit. Alternatively, if the data signal is logically low, then the selector selects another delayed clock signal supplied from the second delay circuit. Then, the delayed clock signal, selected by the selector, is latched in the holding circuit. The input circuit with such a configuration prevents skewing from being caused by a difference in length between the transition interval of the data signal from H into L level and that of the data signal from L into H level. As a result, data can be transferred at a much higher speed even if the clock frequency is very high.

摘要翻译： 输入电路包括：比较器; 第一和第二延迟电路; 选择器 一个输入缓冲区; 和保持电路。 比较器将从输入缓冲器提供的数据信号的前沿和/或后沿比较到要锁存数据信号的时钟信号的边沿。 基于比较结果，第一和第二延迟电路分别延迟时钟信号预定的时间量。 如果数据信号逻辑高，则选择器选择从第一延迟电路提供的延迟时钟信号。 或者，如果数据信号在逻辑上低，则选择器选择从第二延迟电路提供的另一延迟时钟信号。 然后，由选择器选择的延迟时钟信号被锁存在保持电路中。 具有这种配置的输入电路防止由数据信号从H变为L电平的过渡间隔和从L变为H电平的数据信号之间的长度差引起的偏移。 因此，即使时钟频率非常高，也可以以更高的速度传输数据。

公开(公告)号：US06711086B2

公开(公告)日：2004-03-23

申请号：US10271829

申请日：2002-10-15

申请人： Yutaka Terada

发明人： Yutaka Terada

IPC分类号： G11C816

CPC分类号： G11C8/16

摘要： A semiconductor memory having ports, each of which conducts exclusively a writing or reading operation, by which the access operation can be speeded up when cells at the same row address are accessed simultaneously through two ports. A current-carrying capability of a write access transistor making up a memory cell is lowered relative to a current-carrying capability of a read access transistor within a range capable of finishing the writing operation.

摘要翻译： 一种具有端口的半导体存储器，每个端口都进行专门的写入或读取操作，当通过两个端口同时访问相同行地址的单元时，可以加速访问操作。 构成存储单元的写入存取晶体管的载流能力相对于能够完成写入操作的范围内的读取存取晶体管的载流能力降低。

公开(公告)号：US06255863B1

公开(公告)日：2001-07-03

申请号：US09573827

申请日：2000-05-18

申请人： Hiroyuki Yamauchi ,  Yutaka Terada

发明人： Hiroyuki Yamauchi ,  Yutaka Terada

IPC分类号： H03K522

CPC分类号： H04L25/0272 ,  H03K5/007 ,  H03K5/082 ,  H03K5/2481 ,  H04L25/028 ,  H04L25/062

摘要： The level of a differential signal is determined such that a system, utilizing the level determined, can operate stably enough even if the intermediate potential of the signal changes. A comparator receives, as differential input, a differential signal to be transmitted. During a level determination interval, a sampler/level determiner samples the output of the comparator a number of times, and outputs a most frequently sampled value as the level of the differential signal.

摘要翻译： 确定差分信号的电平，使得即使信号的中间电位改变，利用所确定的电平的系统也能够稳定地工作。 比较器作为差分输入端接收待发送的差分信号。 在电平确定间隔期间，采样器/电平确定器多次对比较器的输出进行采样，并输出最频繁采样的值作为差分信号的电平。

公开(公告)号：US06172557B2

公开(公告)日：2001-01-09

申请号：US09398817

申请日：1999-09-20

申请人： Yutaka Terada ,  Keiichi Kusumoto ,  Akira Matsuzawa

发明人： Yutaka Terada ,  Keiichi Kusumoto ,  Akira Matsuzawa

IPC分类号： H03D300

CPC分类号： G04F10/005 ,  G01R29/027 ,  H03D3/04 ,  H03K9/06

摘要： Provided is a time counting circuit which can measure the time taken from the rising edge to the falling edge of a pulse signal and the time from the falling edge to the rising edge thereof. The time counting circuit according to the present invention comprises a measuring circuit for measuring the time between either of the rising and falling edges of the pulse signal, and a pulse converting circuit for converting a pulse signal to be measured to a pulse signal having either of the edges in accordance with the rising edge of the pulse signal to be measured and having either of the edges in accordance with the falling edge of the pulse signal to be measured. The time between either of the edges of the pulse signal converted by the pulse converting circuit is measured by the measuring circuit. The time obtained by measurement is the time taken from the rising edge to the falling edge of the pulse signal to be measured or the time taken from the falling edge to the rising edge thereof.

摘要翻译： 提供了一种时间计数电路，其可以测量从脉冲信号的上升沿到下降沿的时间以及从下降沿到上升沿的时间。 根据本发明的计时电路包括：测量脉冲信号的上升沿和下降沿之间的时间的测量电路;以及脉冲转换电路，用于将要测量的脉冲信号转换成具有 根据要测量的脉冲信号的上升沿的边缘，并根据要测量的脉冲信号的下降沿具有任一边缘。 由脉冲转换电路转换的脉冲信号的任一边之间的时间由测量电路测量。 通过测量获得的时间是从要测量的脉冲信号的上升沿到下降沿或从下降沿到其上升沿的时间所花费的时间。

公开(公告)号：US5216217A

公开(公告)日：1993-06-01

申请号：US821808

申请日：1992-01-17

申请人： Hiroaki Morishita ,  Yutaka Terada ,  Kazuo Tsurumoto ,  Akiyasu Ito

发明人： Hiroaki Morishita ,  Yutaka Terada ,  Kazuo Tsurumoto ,  Akiyasu Ito

IPC分类号： B23H7/02 ,  B23H7/10

CPC分类号： B23H7/104

摘要： Accurate control of the tension of a wire electrode in a wirecut electrical discharge machine is achieved by eliminating a direct-current (DC) component from a speed difference signal between a braking section and a recovery section of the machine. The DC component of the speed signal which is eliminated is associated with the stretching of the wire electrode while under tension. As a result, the tension can be maintained constant dynamically as well as statically, thereby improving machining accuracy.

公开(公告)号：US5212256A

公开(公告)日：1993-05-18

申请号：US610205

申请日：1990-11-08

申请人： Yukio Mizuno ,  Takashi Maruyama ,  Hiroomi Abe ,  Yutaka Terada

发明人： Yukio Mizuno ,  Takashi Maruyama ,  Hiroomi Abe ,  Yutaka Terada

IPC分类号： C08L61/20 ,  C08L71/12 ,  C08L77/00

CPC分类号： C08L71/123 ,  C08L77/00 ,  C08L61/20 ,  Y10S525/905

摘要： The present invention provides a thermoplastic resin composition which is improved in compatibility between polyphenylene ether and polyamide and is excellent in processability and impact strength. This composition comprises:(A) 100 parts by weight of a composition comprising 95-5% by weight of a polyphenylene ether obtained by oxidation polymerization of one or more of phenol compounds represented by the following formula: ##STR1## (wherein R.sub.1, R.sub.2, R.sub.3, R.sub.4 and R.sub.5 which may be identical or different, each represents a hydrogen atom, a halogen atom, a hydrocarbon radical or a substituted hydrocarbon radical and at least one of them is a hydrogen atom) and 5-95% by weight of a polyamide,(B) 0-30 parts by weight of an impact strength modifier, and(C) 0.01-10 parts by weight of an amino resin obtained by modifying with an alcohol an addition reaction product of formaldehyde and at least one compound selected from the group consisting of melamine, guanamine and urea.

摘要翻译： 本发明提供一种提高聚苯醚和聚酰胺之间的相容性并且加工性和冲击强度优异的热塑性树脂组合物。 该组合物包含：（A）100重量份的组合物，其包含95-5重量％的通过氧化聚合一种或多种下式表示的酚化合物获得的聚苯醚：其中R1，R2 可以相同或不同的R 3，R 4和R 5各自表示氢原子，卤素原子，烃基或取代烃基，并且其中至少一个为氢原子）和5-95重量％ 聚酰胺，（B）0-30重量份的冲击强度改性剂，和（C）0.01-10重量份通过用醇改性得到的氨基树脂，所述加成反应产物与所选择的至少一种化合物 由三聚氰胺，胍胺和尿素组成。