公开(公告)号：US06694601B2

公开(公告)日：2004-02-24

申请号：US09590625

申请日：2000-06-08

Applicant: Haruo Matsumoto ,  Yasuo Yamada ,  Yukihiro Kitaichi ,  Tadahiro Yorita ,  Hideyuki Kato ,  Tatsuya Tsujiguchi ,  Hisashi Mori ,  Hitoshi Tada

Inventor： Haruo Matsumoto ,  Yasuo Yamada ,  Yukihiro Kitaichi ,  Tadahiro Yorita ,  Hideyuki Kato ,  Tatsuya Tsujiguchi ,  Hisashi Mori ,  Hitoshi Tada

IPC: H01P1205

CPC classification number: H01P1/2056 ,  Y10T29/49016

Abstract: A method of adjusting characteristics of a dielectric filter including the following steps: forming a dielectric filter having a dielectric body, the dielectric body having an outer surface; forming an external conductor on the outer surface of the dielectric body; and forming at least one hole extending through the dielectric body, the at least one hole having a respective inner surface, and a respective internal conductor and a respective non-conductive portion at the inner surface; the outer surface of the dielectric body comprising first and second end surfaces and a side surface extending between the first and second end surfaces; the at least one hole extending through the dielectric body between the first and second end surfaces; the respective inner conductor being formed as a respective pair of internal conductors conductively connected to the external conductor at respective ends of the at least one hole, the respective non-conductive portion at the inner surface of the at least one hole being spaced from both end surfaces, thereby separating the corresponding pair of internal conductors and defining a respective capacitance between the corresponding pair of internal conductors; and a predetermined portion of the outer surface of the dielectric body being formed with a shape such that a first portion of the external conductor at the predetermined portion of the outer surface is closer to at least one of the internal conductors in the at least one hole as compared with a second portion of the external conductor at a portion of the outer surface of the dielectric body other than the predetermined portion; the method further comprising the steps of: initially forming the respective inner conductor over an entire length of the inner surface of the corresponding hole; and thereafter grinding off a portion of the respective inner conductor with a grinding tool in order to form the non-conductive portion.

Abstract translation: 一种调整介质滤波器的特性的方法，包括以下步骤：形成具有电介质体的介电滤波器，所述电介质体具有外表面; 在绝缘体的外表面上形成外部导体; 以及形成延伸穿过所述电介质体的至少一个孔，所述至少一个孔具有相应的内表面，以及相应的内部导体和在所述内表面处的相应的非导电部分; 电介质体的外表面包括第一和第二端面以及在第一和第二端面之间延伸的侧表面; 所述至少一个孔延伸穿过所述介电体在所述第一和第二端面之间; 相应的内部导体形成为在所述至少一个孔的相应端部处导电地连接到外部导体的相应的一对内部导体，所述至少一个孔的内表面处的相应的非导电部分与两个端部间隔开 从而分离相应的一对内部导体并且在相应的一对内部导体之间限定相应的电容; 并且所述电介质体的外表面的预定部分形成为使得所述外表面的所述预定部分处的所述外部导体的所述第一部分更靠近所述至少一个孔中的至少一个内部导体 与外部导体的除了预定部分之外的绝缘体外表面的一部分的第二部分相比; 该方法还包括以下步骤：在相应孔的内表面的整个长度上初始形成相应的内部导体; 然后用研磨工具研磨各个内部导体的一部分，以便形成非导电部分。

公开(公告)号：US06556101B1

公开(公告)日：2003-04-29

申请号：US09707264

申请日：2000-11-06

Applicant: Hitoshi Tada ,  Hideyuki Kato ,  Haruo Matsumoto

Inventor： Hitoshi Tada ,  Hideyuki Kato ,  Haruo Matsumoto

IPC: H01P1202

CPC classification number: H01P1/2056 ,  H01P7/04

Abstract: A small-sized low-loss dielectric resonator, dielectric filter, and dielectric duplexer, and a communication device using such an element. Through-holes are formed in a dielectric block. The inner surface of each through-hole is covered with a thin-film multilayer electrode consisting of an outermost conductive layer and a multilayer region including thin-film conductive layers and thin-film dielectric layers. An outer conductor having a similar thin-film multilayer electrode structure is formed on the outer surface of the dielectric block. An outer conductor in the form of a single-layer electrode is formed on a short-circuited end face of the dielectric block thereby connecting together the thin-film conductive layers of the inner and outer conductors.

Abstract translation: 小型低损耗介质谐振器，介质滤波器和介质双工器，以及使用这种元件的通信装置。 在介质块中形成通孔。 每个通孔的内表面被由最外面的导电层和包括薄膜导电层和薄膜电介质层的多层区组成的薄膜多层电极覆盖。 在介质块的外表面上形成具有类似薄膜多层电极结构的外导体。 在介质块的短路端面上形成单层电极形式的外导体，由此将内导体和外导体的薄膜导电层连接在一起。

公开(公告)号：US06359529B1

公开(公告)日：2002-03-19

申请号：US08998252

申请日：1997-12-24

Applicant: Kikuo Tsunoda ,  Hitoshi Tada

Inventor： Kikuo Tsunoda ,  Hitoshi Tada

IPC: H01P1213

CPC classification number: H01P1/2135 ,  H01P1/2136

Abstract: The invention provides a filtering device of the transmission-reception switched type which can be constructed in a form with a reduced size at a low cost without having to use circuit elements such as a capacitor, a coil, and a transmission line forming a phase shift circuit which are not essential to the filtering device. Inner conductors serving as distributed-parameter resonance lines are formed in a dielectric block. There is provided a coupling line coupled with particular inner conductors. The open-circuited ends of these particular inner conductors are connected to an outer conductor via corresponding diode switches so that transmission and reception filters are switched from each other when either diode switch is selectively turned on.

Abstract translation: 本发明提供了一种发送 - 接收切换型滤波装置，其可以以低成本构成尺寸减小的形式，而不必使用诸如电容器，线圈和形成相移的传输线之类的电路元件 电路对滤波装置不是必需的。 用作分布参数谐振线的内导体形成在介质块中。 提供了与特定内部导体耦合的耦合线。 这些特定内部导体的开路端通过相应的二极管开关连接到外部导体，使得当二极管开关选择性地导通时，发射和接收滤波器彼此切换。

公开(公告)号：US6034579A

公开(公告)日：2000-03-07

申请号：US390629

申请日：1995-02-17

Applicant: Hitoshi Tada ,  Tatsuya Tsujiguchi

Inventor： Hitoshi Tada ,  Tatsuya Tsujiguchi

IPC: H01P1/205

CPC classification number: H01P1/2056

Abstract: A dielectric filter is formed by a plurality of resonator holes which are formed in a single dielectric block in such a manner that they extend in a direction between an open-circuited end surface and a short-circuited end surface of the dielectric block. The resonator holes are opened only at the short-circuited end surface. An inner conductor is formed on an inner surface of each of the resonator holes. An outer conductor is formed on an outer surface of the dielectric block. Capacitor electrodes respectively corresponding to the resonator holes are formed on the open-circuited end surface of the dielectric block. Input/output electrodes electrically connected to the capacitor electrodes are formed in such a manner that they extend on both the open-circuited end surface and a bottom surface of the dielectric block. In this structure, since all the capacitive components constituting the filter can be obtained by either the capacitances formed between the capacitor electrodes and the inner conductors, or the capacitances formed in a gap between the capacitor electrodes, the dielectric filter can be constructed in the form of a single block.

Abstract translation: 介质滤波器由多个谐振器孔形成，它们形成在单个介电块中，使得它们沿介质块的开路端面和短路端面之间的方向延伸。 谐振器孔只在短路端面打开。 内导体形成在每个谐振器孔的内表面上。 外导体形成在介质块的外表面上。 分别对应于谐振器孔的电容器电极形成在介质块的开路端面上。 电连接到电容器电极的输入/输出电极以这样的方式形成，使得它们在介电块的开路端面和底表面上延伸。 在这种结构中，由于可以通过形成在电容器电极和内部导体之间的电容或形成在电容器电极之间的间隙中的电容来获得构成滤波器的所有电容性分量，所以可以以 的单块。

公开(公告)号：US6014067A

公开(公告)日：2000-01-11

申请号：US839410

申请日：1997-04-14

Applicant: Haruo Matsumoto ,  Yasuo Yamada ,  Yukihiro Kitaichi ,  Tadahiro Yorita ,  Hideyuki Kato ,  Tatsuya Tsujiguchi ,  Hisashi Mori ,  Hitoshi Tada

Inventor： Haruo Matsumoto ,  Yasuo Yamada ,  Yukihiro Kitaichi ,  Tadahiro Yorita ,  Hideyuki Kato ,  Tatsuya Tsujiguchi ,  Hisashi Mori ,  Hitoshi Tada

IPC: H01P1/205 ,  H01P1/202

CPC classification number: H01P1/2056 ,  Y10T29/49016

Abstract: Dielectric resonator wherein an internal conductor non-formed portion is provided near one open face of the internal conductor formed holes, and signal input, output electrodes are provided on one portion of the external conductor, whereby electromagnetic field leakage is restrained, because the open face is not formed, and individual parts such as signal input, output pins and so on are not required.

Abstract translation: 介质谐振器，其中内部导体非形成部分设置在内部导体形成的孔的一个开放面附近，并且信号输入，输出电极设置在外部导体的一部分上，由此电磁场泄漏被限制，因为开放面 没有形成，不需要信号输入，输出引脚等各个部件。

公开(公告)号：US5786234A

公开(公告)日：1998-07-28

申请号：US873459

申请日：1997-06-12

Applicant: Yutaka Nagai ,  Hitoshi Tada

Inventor： Yutaka Nagai ,  Hitoshi Tada

IPC: H01S5/00 ,  H01S5/20 ,  H01S5/223 ,  H01S5/323 ,  H01L21/00

CPC classification number: H01S5/2231 ,  H01S5/209 ,  H01S5/32316 ,  Y10S438/955

Abstract: A method of fabricating a semiconductor laser includes successively epitaxially growing on a first conductivity type semiconductor substrate, a first conductivity type lower cladding layer, an active layer, a second conductivity type first upper cladding layer having a relatively high etching rate in an etchant, a second conductivity type etch stopping layer having a relatively low etching rate in the etchant, a second conductivity type second upper cladding layer, and a second conductivity type first contact layer; forming a stripe-shaped mask on the first contact layer; removing portions of the first contact layer and the second upper cladding layer in a first wet etching step to expose the etch stopping layer; removing portions of the second upper cladding layer in a second wet etching step to form a stripe-shaped ridge structure having a reverse mesa cross section without an intermediate construction; growing a first conductivity type current blocking layer contacting both sides of the ridge structure; and after removal of the mask, growing a second conductivity type second contact layer on the current blocking layer and on the first contact layer. The angle between the side wall of the ridge and the etch stopping layer is an acute angle so the stripe-shaped ridge structure has a perfect reverse mesa cross section and is narrowest proximate the active layer.

Abstract translation: 制造半导体激光器的方法包括在蚀刻剂上具有相对较高蚀刻速率的第一导电型半导体衬底，第一导电型下包层，有源层，第二导电类型的第一上敷层， 第二导电型蚀刻停止层，在蚀刻剂中具有相对低的蚀刻速率，第二导电类型的第二上覆层和第二导电类型的第一接触层; 在所述第一接触层上形成条形掩模; 在第一湿蚀刻步骤中去除第一接触层和第二上包层的部分以暴露蚀刻停止层; 在第二湿蚀刻步骤中去除第二上包层的部分，以形成具有不具有中间结构的反台面横截面的条形脊结构; 生长接触脊结构两侧的第一导电型电流阻挡层; 并且在去除掩模之后，在电流阻挡层和第一接触层上生长第二导电类型的第二接触层。 脊的侧壁与蚀刻停止层之间的角度是锐角，因此条形脊结构具有完美的逆台面横截面，并且在有源层附近最窄。

公开(公告)号：US5712604A

公开(公告)日：1998-01-27

申请号：US469443

申请日：1995-06-06

Applicant: Hitoshi Tada ,  Hideyuki Kato ,  Haruo Matsumoto ,  Tatsuya Tsujiguchi

Inventor： Hitoshi Tada ,  Hideyuki Kato ,  Haruo Matsumoto ,  Tatsuya Tsujiguchi

IPC: H01P1/205 ,  H01P1/20

CPC classification number: H01P1/2056

Abstract: A single-stage dielectric band elimination filter has a dielectric block with its outer surfaces mostly covered by an outer conductor and two mutually coupled resonant lines formed therein. Each resonant line has an open end insulated from the outer conductor and a shorted end connected thereto, the open and shorted ends of the two resonant lines being oppositely oriented. A multi-stage dielectric filter has a plurality of such single-stage band elimination filters formed inside a dielectric block, each mutually adjacent pair of the single-stage band elimination filters being interdigitally coupled or combline-coupled to each other with phase shift of II/2 therebetween. The open end of a resonant line may be formed at one of the end surfaces of the dielectric block, being connected to an electrode insulated from the outer conductor, or at an annular conductor-free area formed on the inner surface of the corresponding throughhole. The resonant lines for forming the plurality of single-stage band elimination filters may be arranged horizontally or vertically with respect to each other. Screening electrodes may be inserted between mutually adjacent resonant lines.

Abstract translation: 单级介质带除滤波器具有介电块，其外表面主要被外导体覆盖，并且形成有两个相互耦合的谐振线。 每个谐振线路具有与外部导体绝缘的开口端和与其连接的短路端，两个谐振线路的开路端和短路端相对定向。 多级介质滤波器具有形成在介质块内部的多个这样的单级带除滤波器，每个相互相邻的单级带除滤波器对被互相连接或组合耦合，具有II相位 / 2。 谐振线路的开口端可以形成在介质块的一个端面上，连接到与外部导体绝缘的电极，或形成在相应通孔的内表面上的环形无导体区域。 用于形成多个单级带除滤波器的谐振线路可以相对于彼此水平或垂直布置。 屏蔽电极可以插入相互相邻的谐振线之间。

公开(公告)号：US5684902A

公开(公告)日：1997-11-04

申请号：US677208

申请日：1996-07-09

Applicant: Hitoshi Tada

Inventor： Hitoshi Tada

IPC: G02B6/42 ,  H01L25/04 ,  H01L25/18 ,  H01S5/00 ,  H01S5/022 ,  G02B6/36

CPC classification number: G02B6/423 ,  H01S5/02252 ,  G02B6/4224 ,  H01S5/0207 ,  H01S5/02244 ,  H01S5/2275

Abstract: In a semiconductor laser module wherein a semiconductor laser chip having a light emitting facet and an optical fiber having a fiber facet are mounted on a module substrate so that the light emitting facet faces the fiber facet, the semiconductor laser chip includes semiconductor layers disposed on a semiconductor substrate and including a light emitting region, and the semiconductor substrate has a portion protruding beyond the light emitting facet. The optical fiber includes a core extending in the optical waveguide direction and a cladding part surrounding the core. In this module, positioning of the optical fiber in the optical axis direction is performed by abutting a portion of the cladding part at the fiber facet against the protruding portion of the substrate of the semiconductor laser chip. Therefore, alignment of the optical fiber with the laser chip in the optical axis direction is performed easily and accurately with a desired spacing between them, without contacting the light emitting facet of the laser chip to the fiber facet, whereby coupling efficiency between the laser chip and the optical fiber is significantly improved.

Abstract translation: 在其中具有发光面的半导体激光器芯片和具有光纤面的光纤的半导体激光器模块安装在模块基板上，使得发光小面面向光纤面，半导体激光器芯片包括设置在光纤面上的半导体层 半导体衬底并且包括发光区域，并且所述半导体衬底具有突出超过所述发光小面的部分。 光纤包括沿光波导方向延伸的芯和围绕芯的包层部。 在该模块中，通过使光纤面上的包层部的一部分抵靠半导体激光芯片的基板的突出部而使光纤在光轴方向上的定位。 因此，光纤与激光芯片的光轴方向的对准以其间的期望的间隔容易且准确地进行，而不会将激光芯片的发光面与光纤面相接触，由此激光芯片 光纤显着改善。

公开(公告)号：US5668822A

公开(公告)日：1997-09-16

申请号：US493545

申请日：1995-06-22

Applicant: Hitoshi Tada

Inventor： Hitoshi Tada

IPC: H01S5/00 ,  H01S5/024 ,  H01S5/40 ,  H01S3/04

CPC classification number: H01S5/02272 ,  H01S5/02236 ,  H01S5/024 ,  H01S5/4031 ,  H01S5/02252 ,  H01S5/02276 ,  H01S5/4018 ,  H01S5/4037

Abstract: A method of fabricating an integrated semiconductor laser device includes preparing a polygonal heat sink having side surfaces, and die-bonding semiconductor laser chips to the side surfaces of the heat sink. Therefore, the semiconductor laser chips are accurately arranged at such positions that laser beams emitted from these laser chips are parallel to each other and partially overlap each other. In addition, the semiconductor laser chips are integrated without unwanted contact of a conductive material used for the die-bonding to an active layer exposed at a facet of each laser chip. Further, since the complicated process of die-bonding a laser chip on another laser chip is dispensed with, the fabricating method is easily automated.

Abstract translation: 一种制造集成半导体激光器件的方法包括制备具有侧表面的多边形散热器，并将半导体激光芯片芯片接合到散热器的侧表面。 因此，半导体激光芯片精确地布置在这些位置上，使得从这些激光芯片发射的激光束彼此平行并且部分地彼此重叠。 此外，将半导体激光芯片集成在一起，而不用用于芯片接合的导电材料与暴露在每个激光芯片的小面处的有源层接触。 此外，由于省去了将激光芯片芯片接合在另一激光芯片上的复杂工艺，所以制造方法容易自动化。

公开(公告)号：US5585309A

公开(公告)日：1996-12-17

申请号：US327841

申请日：1994-10-17

Applicant: Kenzo Mori ,  Tadashi Kimura ,  Yoshitatu Kawama ,  Nobuaki Kaneno ,  Tatuya Kimura ,  Yuji Okura ,  Hitoshi Tada

Inventor： Kenzo Mori ,  Tadashi Kimura ,  Yoshitatu Kawama ,  Nobuaki Kaneno ,  Tatuya Kimura ,  Yuji Okura ,  Hitoshi Tada

IPC: H01S5/00 ,  H01S5/20 ,  H01S5/22 ,  H01S5/227 ,  H01S5/323 ,  H01L21/20

CPC classification number: H01S5/227 ,  H01S5/2059 ,  H01S5/2081 ,  H01S5/209 ,  H01S5/2201 ,  H01S5/2205 ,  H01S5/2206 ,  H01S5/2272 ,  H01S5/2275 ,  H01S5/32391 ,  Y10S148/095

Abstract: A method for fabricating a semiconductor laser includes forming a double heterojunction structure on a first conductivity type semiconductor substrate; forming the double heterojunction structure into a stripe mesa shape by selective etching; successively growing a first conductivity type layer, a second conductivity type current blocking layer, and a first conductivity type current blocking layer on opposite sides of the mesa to embed the mesa; and adding an impurity from a surface of the first conductivity type current blocking layer to form impurity doped regions that electrically separate the second conductivity type current blocking layer from an upper part of the mesa at opposite sides of the mesa.

Abstract translation: 一种制造半导体激光器的方法包括在第一导电型半导体衬底上形成双异质结结构; 通过选择性蚀刻将双异质结结构形成条状台面形状; 在台面的相对侧依次生长第一导电型层，第二导电型电流阻挡层和第一导电型电流阻挡层，以嵌入台面; 以及从所述第一导电型电流阻挡层的表面添加杂质，以形成将所述第二导电型电流阻挡层与所述台面的相对侧的所述台面的上部电分离的杂质掺杂区域。