公开(公告)号：US20100268853A1

公开(公告)日：2010-10-21

申请号：US12784238

申请日：2010-05-20

申请人： HakJune OH ,  Hong Beom Pyeon ,  Jin-Ki Kim

发明人： HakJune OH ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC分类号： G06F13/28 ,  G06F3/00

CPC分类号： G11C7/10 ,  G06F13/1689

摘要： A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver.

摘要翻译： 系统控制器与串行互连中的设备通信。 系统控制器发送读取命令，标识串行互连中的目标设备的设备地址和存储器位置。 目标设备响应读取命令以读取由存储器位置识别的位置中的数据。 读取数据被提供为从串行互连中的最后一个设备发送到控制器的数据接收器的输出信号。 考虑到串行互连中的总流通延迟，数据接收器建立与时钟有关的采集时刻。 在每个设备具有时钟同步器的情况下，通过串行互连的传播时钟信号用于建立采集时刻。 考虑到流通延迟，响应于建立的采集时刻来读取数据被锁存，有效数据被锁存在数据接收器中。

公开(公告)号：US07796462B2

公开(公告)日：2010-09-14

申请号：US12034686

申请日：2008-02-21

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C8/00

CPC分类号： G06F13/4291 ,  B60R1/0617

摘要： A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller.

摘要翻译： 系统包括与存储器控制器通信的存储器控​​制器和串联连接的多个存储器件。 每个存储器件具有用于接收和发送数据的多个独立串行端口。 存储器控制器用于指定执行命令的设备的设备地址（DA）或ID号。 由存储器控制器发送的命令中包含的数据由单独的链路控制电路捕获，以响应具有适当延迟的内部生成的时钟。 捕获的数据被写入对应的存储体。 根据由存储器控制器发出的地址来读取存储在一个存储器件的多个存储器组之一中的数据。 读取的数据从存储器件通过串联连接的存储器件传播到存储器控制器。

公开(公告)号：US07752364B2

公开(公告)日：2010-07-06

申请号：US11942173

申请日：2007-11-19

申请人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC分类号： G06F13/00 ,  G06F12/00 ,  G11C7/00 ,  H03K19/003

CPC分类号： G11C7/10 ,  G06F13/1689

摘要： A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver.

摘要翻译： 系统控制器与串行互连中的设备通信。 系统控制器发送读取命令，标识串行互连中的目标设备的设备地址和存储器位置。 目标设备响应读取命令以读取由存储器位置识别的位置中的数据。 读取数据被提供为从串行互连中的最后一个设备发送到控制器的数据接收器的输出信号。 考虑到串行互连中的总流通延迟，数据接收器建立与时钟有关的采集时刻。 在每个设备具有时钟同步器的情况下，通过串行互连的传播时钟信号用于建立采集时刻。 考虑到流通延迟，响应于建立的采集时刻来读取数据被锁存，有效数据被锁存在数据接收器中。

公开(公告)号：US07751272B2

公开(公告)日：2010-07-06

申请号：US12025866

申请日：2008-02-05

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C8/00

CPC分类号： G11C19/00

摘要： A system includes a plurality of memory devices connected in-series that communicate with a memory controller. When a memory device receives a command strobe signal indicating the start of a command having an ID number, the memory device is placed in a de-selected state and the ID number is compared to the memory device's device address. Delayed versions of the command strobe signal and the command are forwarded while the memory device is in the de-selected state. If the ID number matches the device address with reference to the ID number, the memory device is placed in a selected state. In the selected state, the memory device may refrain from forwarding the delayed versions of the command strobe signal and the command, such that if there is a match, a truncated part of the command is forwarded before the memory device is placed in the selected state.

摘要翻译： 系统包括与存储器控制器通信的串联连接的多个存储器件。 当存储器装置接收到指示具有ID号的命令的开始的命令选通信号时，将存储器件置于取消选择状态，并将ID号与存储器件的器件地址进行比较。 当存储器件处于取消选择状态时，命令选通信号和命令的延迟版本被转发。 如果ID编号与设备地址相匹配，则将存储设备置于选择状态。 在选择状态下，存储装置可以避免转发命令选通信号和命令的延迟版本，使得如果存在匹配，则在将存储装置置于选择状态之前转发命令的截断部分 。

公开(公告)号：US07747833B2

公开(公告)日：2010-06-29

申请号：US11643850

申请日：2006-12-22

申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

IPC分类号： G06F12/00

CPC分类号： G06F13/4022 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/408

摘要： Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

摘要翻译： 提供了具有多个存储体和多个链接控制器的存储器系统。 对于每个存储体，存在用于接收每个链路控制器的输出并且仅将一个链路控制器的输出传递到存储体的第一切换逻辑。 对于每个链路控制器，存在用于接收每个存储体的输出并且仅将一个存储体的输出传递到链路控制器的第二切换逻辑。 根据本发明的实施例，存在用于控制第一开关逻辑和第二开关逻辑的操作的开关控制器逻辑，以防止多个链路控制器同时或重叠地访问同一存储体，并且用于防止同时或重叠访问 通过相同的链路控制器到多个银行。

公开(公告)号：US20100091538A1

公开(公告)日：2010-04-15

申请号：US12533732

申请日：2009-07-31

申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G11C5/02 ,  G11C7/00 ,  G11C5/06

CPC分类号： G11C5/02 ,  G06F13/4234 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15311

摘要： Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface connected to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

摘要翻译： 公开了用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接器件包括连接到至少一个分立存储器件的本地控制接口，连接到至少一个分立存储器件的本地输入/输出接口以及插入在本地控制接口和本地之间的全局输入/输出接口 输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

公开(公告)号：US07679976B2

公开(公告)日：2010-03-16

申请号：US12391810

申请日：2009-02-24

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C7/00

CPC分类号： G11C29/32 ,  G11C29/003 ,  G11C29/40 ,  G11C2029/0409 ,  G11C2029/2602

摘要： A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices.

摘要翻译： 一种用于在多设备系统中对存储器进行高速测试的方法和系统，其中多设备系统的各个设备被布置成串行互连配置。 通过首先将测试模式数据写入多设备系统的每个设备的存储体，然后进行本地测试读取和每个设备中的数据比较来实现高速测试。 每个设备产生表示设备中不存在或存在故障位位置的本地结果数据。 每个设备中的串行测试电路将本地结果数据与来自先前设备的全局结果数据进行比较。 测试电路压缩此比较的结果，并将其作为更新的全局结果数据提供给下一个设备。 因此，更新的全局结果数据将表示所有先前设备的本地结果数据。

公开(公告)号：US20080209110A1

公开(公告)日：2008-08-28

申请号：US12030235

申请日：2008-02-13

申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC分类号： G06F12/02 ,  G06F12/16

CPC分类号： G06F13/4243 ,  G06F13/4247

摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

摘要翻译： 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

公开(公告)号：US06337816B1

公开(公告)日：2002-01-08

申请号：US09578865

申请日：2000-05-26

申请人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

发明人： San Ha Park ,  Ju Han Kim ,  Hong Beom Pyeon

IPC分类号： G11C700

CPC分类号： G11C29/846 ,  G11C29/785

摘要： The present invention relates to a column redundancy circuit for a semiconductor memory whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The normal data stored in the normal memory cells and the redundancy data stored in the redundancy memory cells are outputted to a switch unit. A column redundancy unit outputs a redundancy enable signal according to a column address, a row address and a fuse short state. According to the logical state of the redundancy enable signal, the switch unit selects the normal data or redundancy data from the memory array, and outputs it to a main amplifier.

摘要翻译： 本发明涉及一种用于半导体存储器的列冗余电路，其存储器阵列被划分成多个阵列单元，以便以高频适当地工作。 存储器阵列中的多个阵列单元包括多个正常存储单元和多个冗余存储单元。 存储在正常存储单元中的正常数据和存储在冗余存储单元中的冗余数据被输出到开关单元。 列冗余单元根据列地址，行地址和熔丝短路状态输出冗余使能信号。 根据冗余使能信号的逻辑状态，开关单元从存储器阵列中选择正常数据或冗余数据，并将其输出到主放大器。

公开(公告)号：US5751170A

公开(公告)日：1998-05-12

申请号：US764386

申请日：1996-12-13

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C29/04 ,  G11C29/50 ,  G01R19/00

CPC分类号： G11C29/50 ,  G11C29/04 ,  G11C7/06 ,  G11C7/065

摘要： A circuit for a low voltage sense amplifier obtains a faster test time in designing a circuit because a conventional sense amplifier adopting voltage 3.3V can be applied to a semiconductor memory device requiring a potential of less than 1.0V, and prevents current leakage at a low threshold voltage by providing source voltage to a sense amplifier of a selected memory cell array in an active mode as well as in a standby mode.

摘要翻译： 用于低电压读出放大器的电路在设计电路时获得更快的测试时间，因为采用3.3V电压的传统读出放大器可以应用于需要小于1.0V电位的半导体存储器件，并且可以防止低电流泄漏 通过向处于活动模式以及待机模式的选定存储单元阵列的读出放大器提供源电压来产生阈值电压。