公开(公告)号：US20090286350A1

公开(公告)日：2009-11-19

申请号：US12509889

申请日：2009-07-27

申请人： Chung Hon Lam ,  Gerhard Ingmar Meijer ,  Alejandro Gabriel Schrott

发明人： Chung Hon Lam ,  Gerhard Ingmar Meijer ,  Alejandro Gabriel Schrott

IPC分类号： H01L21/06 ,  H01L21/34

CPC分类号： H01L45/145 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/32 ,  H01L45/04

摘要： A memory cell for use in integrated circuits comprises a chalcogenide feature and a transition metal oxide feature. Both the chalcogenide feature and transition metal oxide feature each have at least two stable electrical resistance states. At least two bits of data can be concurrently stored in the memory cell by placing the chalcogenide feature into one of its stable electrical resistance states and by placing the transition metal oxide feature into one of its stable electrical resistance states.

摘要翻译： 用于集成电路的存储单元包括硫族化物特征和过渡金属氧化物特征。 硫族化物特征和过渡金属氧化物特征都具有至少两个稳定的电阻状态。 通过将硫族化物特征置于其稳定的电阻状态之一并且将过渡金属氧化物特征置于其稳定的电阻状态之一中，可将至少两位数据同时存储在存储单元中。

公开(公告)号：US20070295948A1

公开(公告)日：2007-12-27

申请号：US11448549

申请日：2006-06-07

申请人： Chung Hon Lam ,  Alejandro Gabriel Schrott

发明人： Chung Hon Lam ,  Alejandro Gabriel Schrott

IPC分类号： H01L47/00

CPC分类号： H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1691

摘要： A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.

摘要翻译： 存储单元包括第一特征和第二特征。 第二特征包括介电材料并限定至少部分地覆盖第一特征的开口。 在第一特征上形成第三特征并且部分地填充第二特征中的开口。 此外，相变材料至少填充第二特征和第三特征之间的体积。 响应于将切换信号施加到存储器单元，相变材料的至少一部分可操作以在较低和较高的电阻状态之间切换。

公开(公告)号：US09082954B2

公开(公告)日：2015-07-14

申请号：US13210020

申请日：2011-08-15

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/16

摘要： An improved phase change memory device has a phase change structure including a thin part between a contact surface of an electrode and a dielectric structure. For example, the thin part has a maximum thickness that is smaller than a maximum width of the contact surface of the electrode. In another example, the phase change structure surrounds the dielectric structure. Several variations improve the contact between the phase change structure and an electrode.

摘要翻译： 改进的相变存储器件具有包括电极的接触表面和电介质结构之间的薄部分的相变结构。 例如，薄部具有比电极的接触表面的最大宽度小的最大厚度。 在另一示例中，相变结构围绕电介质结构。 几种变化改善了相变结构和电极之间的接触。

公开(公告)号：US20100019221A1

公开(公告)日：2010-01-28

申请号：US12177533

申请日：2008-07-22

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： H01L45/00

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1683 ,  Y10S438/90

摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells. Each memory cell in the plurality of memory cells comprises a diode comprising doped semiconductor material and a dielectric spacer on the diode and defining an opening, the dielectric spacer having sides self-aligned with sides of the diode. Each memory cell further comprises a memory element on the dielectric spacer and including a portion within the opening contacting a top surface of the diode.

摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括多个存储器单元。 多个存储单元中的每个存储器单元包括二极管，其包括掺杂半导体材料和二极管上的电介质间隔物，并且限定开口，所述电介质间隔物具有与二极管的侧面自对准的侧面。 每个存储单元还包括介质间隔物上的存储元件，并且包括开口内接触二极管顶表面的部分。

公开(公告)号：US07642125B2

公开(公告)日：2010-01-05

申请号：US11855979

申请日：2007-09-14

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： H01L21/06

CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1683

摘要： An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.

摘要翻译： 通过在触点阵列上形成分离层，在分离层上形成隔离层并使用光刻工艺在隔离层中形成阵列的存储元件开口来制造“蘑菇”型相变存储器单元的阵列。 通过补偿由光刻工艺产生的存储元件开口的尺寸变化的过程，在存储元件开口内形成蚀刻掩模。 蚀刻掩模用于蚀刻穿过分离层以限定电极开口的阵列。 电极材料沉积在电极开口内; 并且存储元件形成在存储元件开口内。 存储元件和底部电极是自对准的。

公开(公告)号：US20090072215A1

公开(公告)日：2009-03-19

申请号：US11855979

申请日：2007-09-14

申请人： Hsiang Lan Lung ,  Chung Hon Lam

发明人： Hsiang Lan Lung ,  Chung Hon Lam

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1683

摘要： An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.

摘要翻译： 通过在触点阵列上形成分离层，在分离层上形成隔离层并使用光刻工艺在隔离层中形成阵列的存储元件开口来制造“蘑菇”型相变存储器单元的阵列。 通过补偿由光刻工艺产生的存储元件开口的尺寸变化的过程，在存储元件开口内形成蚀刻掩模。 蚀刻掩模用于蚀刻穿过分离层以限定电极开口的阵列。 电极材料沉积在电极开口内; 并且存储元件形成在存储元件开口内。 存储元件和底部电极是自对准的。

公开(公告)号：US20090027950A1

公开(公告)日：2009-01-29

申请号：US11828717

申请日：2007-07-26

申请人： Chung Hon Lam ,  Hsiang-Lan Lung

发明人： Chung Hon Lam ,  Hsiang-Lan Lung

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/74

摘要： An embodiment of our invention includes a method of programming at least one phase change memory block, the at least one block comprising at least one phase change memory cell, the at least one cell comprising at least one phase change material. The method includes the steps of transitioning all cells within the at least one block to a first state and, after all cells within the at least one block have been transitioned to the first state, transitioning at least one cell within the at least one block to at least a second state. Transitioning a cell to the at least second state is faster than transitioning a cell to the first state. At least the step of transitioning all cells within the at least one block to a first state may include transitioning all cells within the at least one block in a substantially simultaneous manner.

摘要翻译： 本发明的实施例包括编程至少一个相变存储器块的方法，所述至少一个块包括至少一个相变存储器单元，所述至少一个单元包括至少一个相变材料。 该方法包括以下步骤：将至少一个块内的所有小区转换到第一状态，并且在至少一个块内的所有小区已经转变到第一状态之后，将至少一个块内的至少一个小区转换为 至少第二状态。 将单元转换到至少第二状态比将单元转换到第一状态更快。 至少将至少一个块内的所有小区转换到第一状态的步骤可以包括以基本上同时的方式转换至少一个块内的所有小区。

公开(公告)号：US08350316B2

公开(公告)日：2013-01-08

申请号：US12471287

申请日：2009-05-22

申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

IPC分类号： H01L29/732

CPC分类号： H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.

摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。 多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的相应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻 多行字线中的字线。 相应的字线用作场效应晶体管的栅极。 电介质将对应的字线与沟道区分开。 存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

公开(公告)号：US07932506B2

公开(公告)日：2011-04-26

申请号：US12177533

申请日：2008-07-22

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： H01L29/02

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1683 ,  Y10S438/90

摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells. Each memory cell in the plurality of memory cells comprises a diode comprising doped semiconductor material and a dielectric spacer on the diode and defining an opening, the dielectric spacer having sides self-aligned with sides of the diode. Each memory cell further comprises a memory element on the dielectric spacer and including a portion within the opening contacting a top surface of the diode.

摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括多个存储器单元。 多个存储单元中的每个存储器单元包括二极管，其包括掺杂半导体材料和二极管上的电介质间隔物，并且限定开口，所述电介质间隔物具有与二极管的侧面自对准的侧面。 每个存储单元还包括介质间隔物上的存储元件，并且包括开口内接触二极管顶表面的部分。

公开(公告)号：US07791057B2

公开(公告)日：2010-09-07

申请号：US12107573

申请日：2008-04-22

申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Min Yang ,  Alejandro G. Schrott

发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Min Yang ,  Alejandro G. Schrott

IPC分类号： H01L29/02

CPC分类号： H01L45/143 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/14 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1666

摘要： Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element.

摘要翻译： 描述存储单元以及制造方法。 本文所述的存储单元包括底部电极，其包括基部和基部上的柱部，所述柱部的宽度小于基部的宽度。 电介质围绕底部电极并具有顶部表面。 存储元件覆盖在底部电极上并且包括从电介质的顶表面延伸以与底部电极的柱部分接触的凹部，其中存储元件的凹部具有基本上等于柱的宽度的宽度 部分底部电极。 顶部电极位于存储元件上。