公开(公告)号：US07476580B2

公开(公告)日：2009-01-13

申请号：US11931387

申请日：2007-10-31

申请人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7845 ,  H01L21/28035 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/7842

摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

摘要翻译： 公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。 层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

公开(公告)号：US07476579B2

公开(公告)日：2009-01-13

申请号：US11560925

申请日：2006-11-17

申请人： Huilong Zhu ,  Jing Wang ,  Bruce B. Doris ,  Zhibin Ren

发明人： Huilong Zhu ,  Jing Wang ,  Bruce B. Doris ,  Zhibin Ren

IPC分类号： H01L21/336

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

摘要： A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

摘要翻译： 用于制造的结构和方法包括相邻的PMOSFET和nMOSFET器件，其中栅极叠层各自被在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。

公开(公告)号：US07262087B2

公开(公告)日：2007-08-28

申请号：US10905062

申请日：2004-12-14

申请人： Dureseti Chidambarrao ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Omer H. Dokumaci ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Omer H. Dokumaci ,  Huilong Zhu

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

公开(公告)号：US07220626B2

公开(公告)日：2007-05-22

申请号：US10905978

申请日：2005-01-28

申请人： Huilong Zhu ,  Bruce B. Doris ,  Philip J. Oldiges ,  Meikei Ieong ,  Min Yang ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce B. Doris ,  Philip J. Oldiges ,  Meikei Ieong ,  Min Yang ,  Huajie Chen

IPC分类号： H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1207 ,  Y10S438/938

摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.

摘要翻译： 本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

公开(公告)号：US07098477B2

公开(公告)日：2006-08-29

申请号：US10709248

申请日：2004-04-23

申请人： Huilong Zhu ,  Bruce B. Doris

发明人： Huilong Zhu ,  Bruce B. Doris

IPC分类号： H01L29/036

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： The present invention provides a device structure and method of forming a finFet device having stacked fins. The method of the present invention comprises: providing a substrate with a first semiconductor layer on a first insulator layer, a second insulator layer on the first semiconductor layer, and a second semiconductor layer on the second insulator layer; forming a first fin and a second fin in the second semiconductor layer; masking the first fin; and forming a third fin in the first semiconductor layer, where the second fin is stacked on the third fin. The structure of the present invention comprises: a semiconductor substrate having a first semiconductor layer on a first insulator layer, a second insulator layer on the first semiconductor layer, and a second semiconductor layer on the second insulator layer; a first and second fin formed in the second semiconductor layer; and a third fin formed in the first semiconductor layer, where the second fin is stacked on the third fin.

摘要翻译： 本发明提供一种形成具有堆叠翅片的鳍片装置的装置结构和方法。 本发明的方法包括：在第一绝缘体层上提供具有第一半导体层的衬底，在第一半导体层上提供第二绝缘体层，在第二绝缘体层上提供第二半导体层; 在所述第二半导体层中形成第一鳍片和第二鳍片; 掩蔽第一鳍; 以及在所述第一半导体层中形成第三鳍​​片，其中所述第二鳍片堆叠在所述第三鳍片上。 本发明的结构包括：具有在第一绝缘体层上的第一半导体层，第一半导体层上的第二绝缘体层和第二绝缘体层上的第二半导体层的半导体衬底; 形成在所述第二半导体层中的第一和第二鳍; 以及形成在第一半导体层中的第三鳍，​​其中第二鳍片堆叠在第三鳍片上。

公开(公告)号：US06914303B2

公开(公告)日：2005-07-05

申请号：US10650229

申请日：2003-08-28

申请人： Bruce B. Doris ,  Thomas S. Kanarsky ,  Ying Zhang ,  Huilong Zhu ,  Meikei Ieong ,  Omer Dokumaci

发明人： Bruce B. Doris ,  Thomas S. Kanarsky ,  Ying Zhang ,  Huilong Zhu ,  Meikei Ieong ,  Omer Dokumaci

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6656 ,  H01L29/78612 ,  H01L29/78621

摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

公开(公告)号：US06908850B2

公开(公告)日：2005-06-21

申请号：US10605130

申请日：2003-09-10

申请人： Bruce B. Doris ,  Huilong Zhu

发明人： Bruce B. Doris ,  Huilong Zhu

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/772 ,  H01L29/786 ,  H01I21/4763

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

摘要： A structure and method are provided for fabricating a field effect transistor (FET) having a metal gate structure. A metal gate structure is formed in an opening within a dielectric region formerly occupied by a sacrificial gate. The metal gate structure includes a first layer contacting a gate dielectric formed over a semiconductor region of a substrate. The first layer includes a material selected from the group consisting of metals and metal compounds. The gate further includes a silicide formed over the first layer. The FET further includes a source region and a drain region formed on opposite sides of the gate, the source and drain regions being silicided after the first layer of the gate is formed.

摘要翻译： 提供了一种用于制造具有金属栅结构的场效应晶体管（FET）的结构和方法。 金属栅极结构形成在以前由牺牲栅极占据的电介质区域内的开口中。 金属栅极结构包括与在衬底的半导体区域上形成的栅极电介质接触的第一层。 第一层包括选自金属和金属化合物的材料。 栅极还包括形成在第一层上的硅化物。 FET还包括形成在栅极的相对侧上的源极区域和漏极区域，在形成栅极的第一层之后，源极和漏极区域被硅化。

公开(公告)号：US08669145B2

公开(公告)日：2014-03-11

申请号：US10710272

申请日：2004-06-30

申请人： Bruce B. Doris ,  Diane C. Boyd ,  Huilong Zhu

发明人： Bruce B. Doris ,  Diane C. Boyd ,  Huilong Zhu

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/7842

摘要： A method (and structure) of forming an electronic device includes forming at least one localized stressor region within the device.

摘要翻译： 形成电子器件的方法（和结构）包括在器件内形成至少一个局部应力源区域。

公开(公告)号：US08013392B2

公开(公告)日：2011-09-06

申请号：US11863757

申请日：2007-09-28

申请人： Bruce B. Doris ,  Oleg G. Gluschenkov ,  Huilong Zhu

发明人： Bruce B. Doris ,  Oleg G. Gluschenkov ,  Huilong Zhu

IPC分类号： H01L27/01

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828

摘要： Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.

摘要翻译： 在衬底上形成的半导体结构和形成半导体的工艺。 半导体包括具有场效应晶体管（FETS）的第一部分和场效应晶体管的第二部分的多个场效应晶体管。 第一应力层具有第一厚度并且被配置为向多个场效应晶体管的第一部分施加第一确定的应力。 第二应力层具有第二厚度，并且被配置为将第二确定的应力赋予多个场效应晶体管的第二部分。

公开(公告)号：US07785943B2

公开(公告)日：2010-08-31

申请号：US11928787

申请日：2007-10-30

申请人： Bruce B. Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

发明人： Bruce B. Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Method for providing a transistor that includes the steps of providing a silicon on insulator layer, providing a silicon oxide insulation layer, providing a dielectric layer, removing at least a portion of the silicon oxide insulation layer and the dielectric layer to form a gate stack, and forming a gate electrode. The gate electrode covers a portion of the gate stack.

摘要翻译： 一种用于提供晶体管的方法，包括以下步骤：提供绝缘体上硅层，提供氧化硅绝缘层，提供电介质层，去除氧化硅绝缘层和电介质层的至少一部分以形成栅叠层; 并形成栅电极。 栅电极覆盖栅叠层的一部分。