公开(公告)号：US07271043B2

公开(公告)日：2007-09-18

申请号：US11037622

申请日：2005-01-18

申请人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen ,  Patricia M. Mooney ,  Stephen W. Bedell

发明人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen ,  Patricia M. Mooney ,  Stephen W. Bedell

IPC分类号： H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

摘要： The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

摘要翻译： 本发明提供了具有多个结晶取向的应变Si直接绝缘体（SSDOI）基板及其形成方法。 广义上，但是具体来说，本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层，所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向，并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。 第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

公开(公告)号：US20110195581A1

公开(公告)日：2011-08-11

申请号：US13071940

申请日：2011-03-25

申请人： Bruce B. Doris ,  Haining Yang ,  Huilong Zhu

发明人： Bruce B. Doris ,  Haining Yang ,  Huilong Zhu

IPC分类号： H01L21/31

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7843

摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

摘要翻译： 在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率， 取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。 因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

公开(公告)号：US07691482B2

公开(公告)日：2010-04-06

申请号：US11473835

申请日：2006-06-23

申请人： Huilong Zhu ,  Bruce B. Doris ,  Meikei Ieong ,  Philip J. Oldiges ,  Min Yang

发明人： Huilong Zhu ,  Bruce B. Doris ,  Meikei Ieong ,  Philip J. Oldiges ,  Min Yang

IPC分类号： B32B9/04 ,  H01L27/12

CPC分类号： H01L21/76254 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785 ,  Y10T428/249921 ,  Y10T428/249922

摘要： The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

摘要翻译： 本发明提供一种形成具有多个结晶取向的基本上平面的SOI衬底的方法，包括以下步骤：在单个取向层的顶部提供多个取向表面，所述多个取向表面包括与第一器件区域接触并具有与 单取向层和通过绝缘材料与第一器件区域和单取向层分离的第二器件区域，其中第一器件区域和第二器件区域具有不同的晶体取向; 在单取向层产生损坏的界面; 将晶片接合到所述多个取向表面; 在损坏的界面处分离单个取向层; 其中所述单取向层的损伤表面保留; 以及平坦化损坏的表面，直到第一器件区域的表面基本上与第二器件区域的表面共面。

公开(公告)号：US20090149010A1

公开(公告)日：2009-06-11

申请号：US12352504

申请日：2009-01-12

申请人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

IPC分类号： H01L21/18

CPC分类号： H01L29/7845 ,  H01L21/28035 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/7842

摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi (strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

摘要翻译： 公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。 层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

公开(公告)号：US07476580B2

公开(公告)日：2009-01-13

申请号：US11931387

申请日：2007-10-31

申请人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce B. Doris ,  Huajie Chen

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7845 ,  H01L21/28035 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/7842

摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.

摘要翻译： 公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。 层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

公开(公告)号：US07476579B2

公开(公告)日：2009-01-13

申请号：US11560925

申请日：2006-11-17

申请人： Huilong Zhu ,  Jing Wang ,  Bruce B. Doris ,  Zhibin Ren

发明人： Huilong Zhu ,  Jing Wang ,  Bruce B. Doris ,  Zhibin Ren

IPC分类号： H01L21/336

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

摘要： A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

摘要翻译： 用于制造的结构和方法包括相邻的PMOSFET和nMOSFET器件，其中栅极叠层各自被在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。

公开(公告)号：US07262087B2

公开(公告)日：2007-08-28

申请号：US10905062

申请日：2004-12-14

申请人： Dureseti Chidambarrao ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Omer H. Dokumaci ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Omer H. Dokumaci ,  Huilong Zhu

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

公开(公告)号：US07220626B2

公开(公告)日：2007-05-22

申请号：US10905978

申请日：2005-01-28

申请人： Huilong Zhu ,  Bruce B. Doris ,  Philip J. Oldiges ,  Meikei Ieong ,  Min Yang ,  Huajie Chen

发明人： Huilong Zhu ,  Bruce B. Doris ,  Philip J. Oldiges ,  Meikei Ieong ,  Min Yang ,  Huajie Chen

IPC分类号： H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1207 ,  Y10S438/938

摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.

摘要翻译： 本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

公开(公告)号：US07098477B2

公开(公告)日：2006-08-29

申请号：US10709248

申请日：2004-04-23

申请人： Huilong Zhu ,  Bruce B. Doris

发明人： Huilong Zhu ,  Bruce B. Doris

IPC分类号： H01L29/036

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： The present invention provides a device structure and method of forming a finFet device having stacked fins. The method of the present invention comprises: providing a substrate with a first semiconductor layer on a first insulator layer, a second insulator layer on the first semiconductor layer, and a second semiconductor layer on the second insulator layer; forming a first fin and a second fin in the second semiconductor layer; masking the first fin; and forming a third fin in the first semiconductor layer, where the second fin is stacked on the third fin. The structure of the present invention comprises: a semiconductor substrate having a first semiconductor layer on a first insulator layer, a second insulator layer on the first semiconductor layer, and a second semiconductor layer on the second insulator layer; a first and second fin formed in the second semiconductor layer; and a third fin formed in the first semiconductor layer, where the second fin is stacked on the third fin.

摘要翻译： 本发明提供一种形成具有堆叠翅片的鳍片装置的装置结构和方法。 本发明的方法包括：在第一绝缘体层上提供具有第一半导体层的衬底，在第一半导体层上提供第二绝缘体层，在第二绝缘体层上提供第二半导体层; 在所述第二半导体层中形成第一鳍片和第二鳍片; 掩蔽第一鳍; 以及在所述第一半导体层中形成第三鳍​​片，其中所述第二鳍片堆叠在所述第三鳍片上。 本发明的结构包括：具有在第一绝缘体层上的第一半导体层，第一半导体层上的第二绝缘体层和第二绝缘体层上的第二半导体层的半导体衬底; 形成在所述第二半导体层中的第一和第二鳍; 以及形成在第一半导体层中的第三鳍，​​其中第二鳍片堆叠在第三鳍片上。

公开(公告)号：US06908850B2

公开(公告)日：2005-06-21

申请号：US10605130

申请日：2003-09-10

申请人： Bruce B. Doris ,  Huilong Zhu

发明人： Bruce B. Doris ,  Huilong Zhu

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/772 ,  H01L29/786 ,  H01I21/4763

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

摘要： A structure and method are provided for fabricating a field effect transistor (FET) having a metal gate structure. A metal gate structure is formed in an opening within a dielectric region formerly occupied by a sacrificial gate. The metal gate structure includes a first layer contacting a gate dielectric formed over a semiconductor region of a substrate. The first layer includes a material selected from the group consisting of metals and metal compounds. The gate further includes a silicide formed over the first layer. The FET further includes a source region and a drain region formed on opposite sides of the gate, the source and drain regions being silicided after the first layer of the gate is formed.

摘要翻译： 提供了一种用于制造具有金属栅结构的场效应晶体管（FET）的结构和方法。 金属栅极结构形成在以前由牺牲栅极占据的电介质区域内的开口中。 金属栅极结构包括与在衬底的半导体区域上形成的栅极电介质接触的第一层。 第一层包括选自金属和金属化合物的材料。 栅极还包括形成在第一层上的硅化物。 FET还包括形成在栅极的相对侧上的源极区域和漏极区域，在形成栅极的第一层之后，源极和漏极区域被硅化。