公开(公告)号：US20240021725A1

公开(公告)日：2024-01-18

申请号：US18088546

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Samuel James BADER ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Heli Chetanbhai VORA ,  Ahmad ZUBAIR

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7838 ,  H01L29/66462 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/4236

Abstract: Gallium nitride (GaN) transistors with lateral depletion for integrated circuit technology are described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen above a silicon substrate, a gate structure over the layer including gallium and nitrogen, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, and a source field plate laterally between the gate structure and the drain region, the source field plate laterally separated from the gate structure.

公开(公告)号：US20230066336A1

公开(公告)日：2023-03-02

申请号：US17458112

申请日：2021-08-26

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Kimin JUN ,  Thomas HOFF ,  Han Wui THEN ,  Nicole K. THOMAS ,  Marko RADOSAVLJEVIC ,  Paul B. FISCHER

IPC: H01L27/06 ,  H01L29/26 ,  H01L23/48 ,  H01L49/02 ,  H01L29/778 ,  H01L29/04 ,  H01L21/8258 ,  H01L21/822

Abstract: Gallium nitride (GaN) epitaxy on patterned substrates for integrated circuit technology is described. In an example, an integrated circuit structure includes a material layer including gallium and nitrogen, the material layer having a first side and a second side opposite the first side. A plurality of fins is on the first side of the material layer, the plurality of fins including silicon. A device layer is on the second side of the material layer, the device layer including one or more GaN-based devices.

公开(公告)号：US20230054719A1

公开(公告)日：2023-02-23

申请号：US17408025

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Souvik GHOSH ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Thomas HOFF ,  Ibrahim BAN ,  Kimin JUN ,  Samuel James BADER ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Han Wui THEN

IPC: H01L29/778 ,  H01L29/20

Abstract: Gallium nitride (GaN) layer transfer and regrowth for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate. An insulator layer is over the substrate. A device layer is directly on the insulator layer. The device layer has a thickness of less than approximately 500 nanometers.

公开(公告)号：US20200235216A1

公开(公告)日：2020-07-23

申请号：US16630143

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/423 ,  H01L29/778 ,  H01L29/20 ,  H03F3/193

Abstract: Gallium nitride transistors having multiple threshold voltages are described. In an example, a transistor includes a gallium nitride layer over a substrate, a gate stack over the gallium nitride layer, a source region on a first side of the gate stack, and a drain region on a second side of the gate stack, the second side opposite the first side, wherein the gate stack has a gate length in a first direction extending from the source region to the drain region, the gate stack having a gate width in a second direction perpendicular to the first direction and parallel to the source region and the drain region. The transistor also includes a polarization layer beneath the gate stack and on the GaN layer, the polarization layer having a first portion having a first thickness under a first gate portion and a second thickness under a second gate portion.

公开(公告)号：US20190393319A1

公开(公告)日：2019-12-26

申请号：US16016391

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Sansaptak DASGUPTA ,  Paul FISCHER

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/51 ,  H01L21/285

Abstract: A transistor is disclosed. The transistor includes a first part of a gate above a substrate that has a first width and a second part of the gate above the first part of the gate that is centered with respect to the first part of the gate and that has a second width that is greater than the first width. The first part of the gate and the second part of the gate form a single monolithic T-gate structure.

公开(公告)号：US20190393298A1

公开(公告)日：2019-12-26

申请号：US16017964

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Han Wui THEN

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/66 ,  H01L27/07

Abstract: An integrated circuit structure comprises a first dielectric layer disposed above a substrate. The integrated circuit structure comprises an interconnect structure comprising a first interconnect on a first metal layer, a second interconnect on a second metal layer, and a via connecting the first interconnect and the second interconnect, the first interconnect being on or within the first dielectric layer. A metal-insulator-metal (MIM) capacitor is formed in or on the first dielectric layer in the first metal layer adjacent to the interconnect structure. The MIM capacitor comprises a bottom electrode plate comprising a first low resistivity material, an insulator stack on the bottom electrode plate, the insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer; and a top electrode plate on the insulator stack, the top electrode plate comprising a second low resistivity material.

公开(公告)号：US20190259806A1

公开(公告)日：2019-08-22

申请号：US16347724

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Paul FISCHER ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Edris MOHAMMED

IPC: H01L27/20 ,  H03H3/08 ,  H03H9/02 ,  H03H9/10 ,  H03H9/145 ,  H03H9/25

Abstract: A surface acoustic wave (SAW) resonator structure, an integrated circuit, and a method of fabricating a SAW structure are provided. The method includes epitaxially growing a crystalline aluminum nitride piezoelectric film layer on a substrate; and deposing a plurality of electrodes on the piezoelectric film layer. The SAW structure includes a substrate, a piezoelectric film on the substrate, and a plurality of electrodes on the piezoelectric film.

公开(公告)号：US20190244936A1

公开(公告)日：2019-08-08

申请号：US16386200

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert CHAU ,  Valluri RAO ,  Niloy MUKHERJEE ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Jack KAVALIEROS

IPC: H01L25/07 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8258 ,  H01L29/778 ,  H01L25/00 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L25/072 ,  H01L21/8252 ,  H01L21/8258 ,  H01L25/50 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

公开(公告)号：US20190181099A1

公开(公告)日：2019-06-13

申请号：US16302420

申请日：2016-06-27

Applicant: INTEL CORPORATION

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L23/552 ,  H01P3/00 ,  H01L23/66 ,  H01L27/06 ,  H01L49/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/66 ,  H01P11/00

CPC classification number: H01L23/552 ,  H01L21/8252 ,  H01L23/5225 ,  H01L23/66 ,  H01L27/0605 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2223/6627 ,  H01P3/003 ,  H01P11/003

Abstract: Integrated circuit structures configured with low loss transmission lines are disclosed. The structures are implemented with group III-nitride (III-N) semiconductor materials, and are well-suited for use in radio frequency (RF) applications where high frequency signal loss is a concern. The III-N materials are effectively used as a conductive ground shield between a transmission line and the underlying substrate, so as to significantly suppress electromagnetic field penetration at the substrate. In an embodiment, a group III-N polarization layer is provided over a gallium nitride layer, and an n-type doped layer of indium gallium nitride (InzGa1-zN) is provided over or adjacent to the polarization layer, wherein z is in the range of 0.0 to 1.0. In addition to providing transmission line ground shielding in some locations, the III-N materials can also be used to form one or more active and/or passive components (e.g., power amplifier, RF switch, RF filter, RF diode, etc).

公开(公告)号：US20190172938A1

公开(公告)日：2019-06-06

申请号：US16258422

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz K. GARDNER ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.