公开(公告)号：US20250006738A1

公开(公告)日：2025-01-02

申请号：US18345168

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Nicole K. THOMAS ,  Iulian HETEL ,  Marko RADOSAVLJEVIC

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrating different materials into the channels for stacked transistor devices, for example in a CFET configuration, where the bottom device is an NMOS device and the top device is a PMOS device, or vice versa. Other embodiments may be described and/or claimed.

公开(公告)号：US20240213140A1

公开(公告)日：2024-06-27

申请号：US18088541

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Samuel James BADER ,  Ahmad ZUBAIR ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Heli Chetanbhai VORA ,  Ibrahim BAN ,  Nityan NAIR ,  Thomas HOFF

IPC: H01L23/522 ,  H01L23/48

CPC classification number: H01L23/5223 ,  H01L23/481 ,  H01L23/5226

Abstract: Structures having backside high voltage capacitors for front side GaN-based devices are described. In an example, an integrated circuit structure includes a front side structure including a GaN-based device layer, and one or more metallization layers above the GaN-based device layer. A backside structure is below and coupled to the GaN-based layer, the backside structure including metal layers and one or more alternating laterally-recessed metal insulator metal capacitors.

公开(公告)号：US20240153956A1

公开(公告)日：2024-05-09

申请号：US18409519

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US20210407999A1

公开(公告)日：2021-12-30

申请号：US16913796

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Anh PHAN ,  Nicole K. THOMAS ,  Urusa ALAAN ,  Seung Hoon SUNG ,  Christopher M. NEUMANN ,  Willy RACHMADY ,  Patrick MORROW ,  Hui Jae YOO ,  Richard E. SCHENKER ,  Marko RADOSAVLJEVIC ,  Jack T. KAVALIEROS ,  Ehren MANNEBACH

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US20210167200A1

公开(公告)日：2021-06-03

申请号：US16645119

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN

IPC: H01L29/778 ,  H01L29/417 ,  H01L29/51 ,  H01L21/8252 ,  H01L29/40

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device that may include an III-V transistor with a resistive gate contact. A semiconductor device may include a substrate, and a channel base including a layer of GaN above the substrate. A channel stack may be above the channel base, and may include a layer of GaN in the channel stack, and a polarization layer above the layer of GaN in the channel stack. A gate stack may be above the channel stack, where the gate stack may include a gate dielectric layer above the channel stack, and a resistive gate contact above the gate dielectric layer. The resistive gate contact may include silicon (Si) or germanium (Ge). Other embodiments may be described and/or claimed.

公开(公告)号：US20200227396A1

公开(公告)日：2020-07-16

申请号：US15754822

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sansaptak W. DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Ravi PILLARISETTY ,  Kimin JUN ,  Patrick MORROW ,  Valluri R. RAO ,  Paul B. FISCHER ,  Robert S. CHAU

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00

Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.

公开(公告)号：US20200066893A1

公开(公告)日：2020-02-27

申请号：US16321722

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Pavel M. AGABABOV

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor transistor structure is described. In an example, the semiconductor transistor includes a group III-N semiconductor material disposed on a doped buffer layer, above a substrate. A polarization charge inducing layer is disposed on and conformal with the sloped sidewalls and a planar uppermost surface of the group III-N semiconductor material. A gate structure is disposed on the sloped sidewalls. A source contact is formed on an uppermost portion of the polarization charge inducing layer. A drain region is formed adjacent to the doped buffer layer. An insulator layer is disposed on the drain region and separates the gate structure from the drain region.

公开(公告)号：US20200066890A1

公开(公告)日：2020-02-27

申请号：US16321789

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/08 ,  H01L29/205 ,  H01L29/45 ,  H01L29/66 ,  H01L29/861 ,  H01L27/06

Abstract: A transistor connected diode structure is described. In an example, the transistor connected diode structure includes a group III-N semiconductor material disposed on substrate. A raised source structure and a raised drain structure are disposed on the group III-N semiconductor material. A mobility enhancement layer is disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the mobility enhancement layer, the polarization charge inducing layer having a first portion and a second portion separated by a gap. A gate dielectric layer disposed on the mobility enhancement layer in the gap. A first metal electrode having a first portion disposed on the raised drain structure, a second portion disposed above the second portion of the polarization charge inducing layer and a third portion disposed on the gate dielectric layer in the gap. A second metal electrode disposed on the raised source structure.

公开(公告)号：US20200066849A1

公开(公告)日：2020-02-27

申请号：US16322453

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/20 ,  H01L29/868 ,  H01L29/66 ,  H01L29/205

Abstract: A P-i-N diode structure includes a group III-N semiconductor material disposed on a substrate. An n-doped raised drain structure is disposed on the group III-N semiconductor material. An intrinsic group III-N semiconductor material is disposed on the n-doped raised drain structure. A p-doped group III-N semiconductor material is disposed on the intrinsic group III-N semiconductor material. A first electrode is connected to the p-doped group III-N semiconductor material. A second electrode is electrically coupled to the n-doped raised drain structure. In an embodiment, a group III-N transistor is electrically coupled to the P-i-N diode. In an embodiment, a group III-N transistor is electrically isolated from the P-i-N diode. In an embodiment, a gate electrode and an n-doped raised drain structure are electrically coupled to the n-doped raised drain structure and the second electrode of the P-i-N diode to form the group III-N transistor.

公开(公告)号：US20200058782A1

公开(公告)日：2020-02-20

申请号：US16461353

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/10

Abstract: A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposal adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure.