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公开(公告)号:US11301167B2
公开(公告)日:2022-04-12
申请号:US16414265
申请日:2019-05-16
Applicant: Intel Corporation
Inventor: Jawad B. Khan , Shigeki Tomishima , Srikanth Srinivasan , Chetan Chauhan , Rajesh Sundaram
Abstract: Technologies for providing multiple tier memory media management include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory compute operation. Additionally, the media access circuitry is to read, in response to the request, data from a memory media region of the memory media, write the read data into a compute media region of the memory, perform, on the data in the compute media region, the in-memory compute operation, write, to the memory media region, resultant data indicative of a result of performance of the in-memory compute operation.
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公开(公告)号:US20220075684A1
公开(公告)日:2022-03-10
申请号:US17530281
申请日:2021-11-18
Applicant: Intel Corporation
Inventor: Chetan Chauhan , Wei Wu , Rajesh Sundaram , Shigeki Tomishima
Abstract: Technologies for preserving error correction capability in compute-near-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.
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公开(公告)号:US10678315B2
公开(公告)日:2020-06-09
申请号:US16147950
申请日:2018-10-01
Applicant: Intel Corporation
Inventor: Rajesh Sundaram , Muthukumar P. Swaminathan , Doyle Rivers
IPC: G06F1/20 , G06F1/3234 , G06F1/3225
Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.
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44.
公开(公告)号:US20200019348A1
公开(公告)日:2020-01-16
申请号:US16586428
申请日:2019-09-27
Applicant: Intel Corporation
Inventor: Rajesh Sundaram , Zion S. Kwok , Muthukumar Swaminathan
IPC: G06F3/06
Abstract: Embodiments are directed towards apparatuses, methods, and systems including a pre-read command to eliminate an additional access of read data from a storage location of a memory device. In embodiments, a memory controller issues a pre-read command to store read data in a pre-read latch. In embodiments, the command is issued during a first access of the read data from a storage location in connection with a modify-write operation of the read data. In embodiments, the pre-read latch is located in or coupled to a selected partition of a memory device that includes the storage location that stores the read data. In embodiments, the memory controller subsequently issues a modify-write command to compare the read data stored in the pre-read latch with incoming data, to eliminate a need for a second access of the storage location during completion of the modify-write operation. Additional embodiments may be described and claimed.
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45.
公开(公告)号:US20190310911A1
公开(公告)日:2019-10-10
申请号:US16451545
申请日:2019-06-25
Applicant: Intel Corporation
Inventor: Rajesh Sundaram , Wei Wu , Chetan Chauhan , Srikanth Srinivasan , Shigeki Tomishima
Abstract: Technologies for provisioning error-corrected data for use in in-memory compute operations include a memory that includes a memory media having multiple memory partitions and media access circuitry coupled to the memory media. The media access circuitry is to receive a request to perform an in-memory compute operation on data from the memory media. The request specifies a memory partition of the memory media in which the data is located. The media access circuitry reads the data from the memory partition. The media access circuitry performs error correction on the read data to produce error-corrected read data and stores the error-corrected read data in a temporary buffer for access by one or more in-memory compute operations, in addition to the requested in-memory compute operation.
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46.
公开(公告)号:US20190303237A1
公开(公告)日:2019-10-03
申请号:US16448126
申请日:2019-06-21
Applicant: Intel Corporation
Inventor: Chetan Chauhan , Wei Wu , Rajesh Sundaram , Shigeki Tomishima
Abstract: Technologies for preserving error correction capability in compute-near-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.
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公开(公告)号:US20190227750A1
公开(公告)日:2019-07-25
申请号:US16370007
申请日:2019-03-29
Applicant: Intel Corporation
Inventor: Srikanth Srinivasan , Richard Coulson , Rajesh Sundaram , Bruce Querbach , Jawad B. Khan , Shigeki Tomishima , Sriram Vangal , Wei Wu , Chetan Chauhan
IPC: G06F3/06
Abstract: Technologies for performing tensor operations in memory include a memory comprising media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is to access matrix data from the memory media, perform a tensor operation on the matrix data, and write, to the memory media, resultant data indicative of a result of the tensor operation.
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公开(公告)号:US10324793B2
公开(公告)日:2019-06-18
申请号:US15909929
申请日:2018-03-01
Applicant: Intel Corporation
Inventor: Kiran Pangal , Prashant S. Damle , Rajesh Sundaram , Shekoufeh Qawami , Julie M. Walker , Doyle Rivers
Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
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公开(公告)号:US20170372780A1
公开(公告)日:2017-12-28
申请号:US15645990
申请日:2017-07-10
Applicant: Intel Corporation
Inventor: Shekoufeh Qawami , Rajesh Sundaram , Prashant S. Damle , Doyle Rivers , Julie M. Walker
IPC: G11C13/00
CPC classification number: G11C13/0033 , G06F13/1668 , G11C13/0004 , G11C13/004 , G11C13/0069
Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.
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公开(公告)号:US20160188409A1
公开(公告)日:2016-06-30
申请号:US14844843
申请日:2015-09-03
Applicant: Intel Corporation
Inventor: Kiran Pangal , Prashant S. Damle , Rajesh Sundaram , Shekoufeh Qawami , Julie M. Walker , Doyle Rivers
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1044 , G06F11/1048 , G06F11/1068 , H03M13/05 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/27 , H03M13/6508
Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
Abstract translation: 可以通过确定一组存储器阵列的逻辑阵列地址并且至少部分地基于该组内的至少两个存储器阵列的逻辑位置将逻辑阵列地址变换为至少两个唯一阵列地址来减少不可校正的存储器错误 的存储器阵列。 然后使用至少两个唯一的阵列地址分别访问至少两个存储器阵列。
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