公开(公告)号：US09442868B2

公开(公告)日：2016-09-13

申请号：US14565718

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard A. Uhlig ,  Udo Steinberg ,  Sebastian Schoenberg ,  Sridhar Muthrasanallur ,  Steven M. Bennett ,  Andrew V. Anderson ,  Erik C. Cota-Robles

IPC: G06F9/445 ,  G06F9/46 ,  G06F13/24 ,  G06F13/26 ,  G06F3/00 ,  G06F13/00 ,  G06F9/455 ,  G06F9/48

CPC classification number: G06F13/24 ,  G06F9/45533 ,  G06F9/4812

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

公开(公告)号：US20160019163A1

公开(公告)日：2016-01-21

申请号：US14867025

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/10 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09164901B2

公开(公告)日：2015-10-20

申请号：US14579526

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/02 ,  G06F9/48 ,  G06F12/10 ,  G06F9/455

CPC classification number: G06F12/1036 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4843 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1063 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/30 ,  G06F2212/50 ,  G06F2212/604 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.