公开(公告)号：US20140281629A1

公开(公告)日：2014-09-18

申请号：US13966414

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3278 ,  G06F3/0656 ,  G06F9/3877 ,  G06F9/44 ,  G06F9/4893 ,  G06F13/00 ,  G06F13/1663 ,  G06F2212/312 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section.

公开(公告)号：US20140281403A1

公开(公告)日：2014-09-18

申请号：US13966408

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Thomas W. Fox ,  Bruce M. Fleischer ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F9/30

CPC classification number: G06F9/3867 ,  G06F9/30079 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3826 ,  G06F9/3828

Abstract: Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at a first time, issuing the second sub-instruction at a second time different than the first time, the second time being offset to account for a dependency of the second sub-instruction on a first result from the first sub-instruction, the first pipeline performing the first sub-instruction at a first clock cycle and communicating the first result from performing the first sub-instruction to a chaining bus coupled to the first pipeline and a second pipeline, the communicating at a second clock cycle subsequent to the first clock cycle that corresponds to a total number of latch pipeline stages in the first pipeline.

公开(公告)号：US20140281386A1

公开(公告)日：2014-09-18

申请号：US13795435

申请日：2013-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Thomas W. Fox ,  Bruce M. Fleischer ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30079 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3826 ,  G06F9/3828

Abstract: Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at a first time, issuing the second sub-instruction at a second time different than the first time, the second time being offset to account for a dependency of the second sub-instruction on a first result from the first sub-instruction, the first pipeline performing the first sub-instruction at a first clock cycle and communicating the first result from performing the first sub-instruction to a chaining bus coupled to the first pipeline and a second pipeline, the communicating at a second clock cycle subsequent to the first clock cycle that corresponds to a total number of latch pipeline stages in the first pipeline.

Abstract translation: 实施例包括用于在暴露流水线处理元件中链接数据的方法。 该方法包括将多个指令字分离成第一子指令和第二子指令，在暴露流水线处理元件中接收第一子指令和第二子指令。 该方法还包括在第一时间发出第一子指令，在与第一时间不同的第二时间发出第二子指令，第二时间被补偿以考虑第二子指令对第一子指令的依赖性 来自第一子指令的结果是，第一流水线以第一时钟周期执行第一子指令，并将第一结果从执行第一子指令传送到耦合到第一流水线的链接总线和第二流水线， 在第一时钟周期之后的第二时钟周期中，其对应于第一管线中的锁存流水线级的总数。

公开(公告)号：US20140281100A1

公开(公告)日：2014-09-18

申请号：US13966441

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Martin Ohmacht ,  Krishnan Sugavanam

IPC: G06F13/28

CPC classification number: G06F13/364 ,  G06F9/3826 ,  G06F13/28 ,  G06F21/72 ,  H01L25/18 ,  H01L2924/0002 ,  H04L2209/125 ,  Y02D10/14 ,  H01L2924/00

Abstract: Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.

Abstract translation: 实施例包括用于旁路有源存储器件中的数据的方法。 该方法包括：请求者确定尚未传送给设保者的授权人的传送次数，根据满足阈值的传送次数，向互连网请求旁路路径用于传送，并通过 基于请求的设保人的旁路路径，互连网络根据请求授予设保人的控制权。 该方法还包括互连网络，其基于事件请求对设保人的控制，并且经由互连网络从其他请求者传送延迟的传输，延迟的传送由于授权者先前由请求者控制而延迟，基于控制进行通信 的设保人被改回互连网络。

公开(公告)号：US20140281084A1

公开(公告)日：2014-09-18

申请号：US13837909

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Martin Ohmacht ,  Krishnan Sugavanam

IPC: G06F13/364

CPC classification number: G06F13/364 ,  G06F9/3826 ,  G06F13/28 ,  G06F21/72 ,  H01L25/18 ,  H01L2924/0002 ,  H04L2209/125 ,  Y02D10/14 ,  H01L2924/00

Abstract: Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.

公开(公告)号：US20140149680A1

公开(公告)日：2014-05-29

申请号：US13685816

申请日：2012-11-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  Y02D10/13

Abstract: According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue.

Abstract translation: 根据一个实施例，提供了一种用于在包括与主动存储器设备通信的主处理器的系统中交换数据的方法。 该方法包括主动存储器装置中的处理元件，从主处理器接收指令，并从主处理器上运行的线程接收存储请求，存储请求指定与处理元件相关联的存储器地址。 该方法还包括将存储请求中提供的值存储在处理元件中的队列中，并且处理元件使用来自队列的值来执行指令。

公开(公告)号：US20140136894A1

公开(公告)日：2014-05-15

申请号：US13673221

申请日：2012-11-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair ,  Daniel A. Prener

IPC: G06F11/14

CPC classification number: G06F11/14 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3887 ,  G06F11/1405 ,  G06F12/10 ,  Y02D10/13

Abstract: An aspect includes providing rollback support in an exposed-pipeline processing element. A method for providing rollback support in an exposed-pipeline processing element includes detecting, by rollback support logic, an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error.

Abstract translation: 一个方面包括在暴露流水线处理元件中提供回滚支持。 用于在暴露流水线处理元件中提供回滚支持的方法包括通过回滚支持逻辑来检测与暴露流水线处理元件中的指令的执行相关联的错误。 回滚支持逻辑确定暴露流水线处理元件是否支持指令预定次数循环的重放。 基于确定暴露流水线处理元件支持指令的重放，在暴露流水线处理元件中执行回滚动作以尝试从错误中恢复。

公开(公告)号：US20140136811A1

公开(公告)日：2014-05-15

申请号：US13674520

申请日：2012-11-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  James A. Kahle ,  Jaime H. Moreno ,  Ravi Nair

IPC: G06F12/10

CPC classification number: G06F13/28 ,  Y02D10/14

Abstract: Embodiments relate to loading and storing of data. An aspect includes a method for transferring data in an active memory device that includes memory and a processing element. An instruction is fetched and decoded for execution by the processing element. Based on determining that the instruction is a gather instruction, the processing element determines a plurality of source addresses in the memory from which to gather data elements and a destination address in the memory. One or more gathered data elements are transferred from the source addresses to contiguous locations in the memory starting at the destination address. Based on determining that the instruction is a scatter instruction, a source address in the memory from which to read data elements at contiguous locations and one or more destination addresses in the memory to store the data elements at non-contiguous locations are determined, and the data elements are transferred.

Abstract translation: 实施例涉及加载和存储数据。 一个方面包括用于在包括存储器和处理元件的活动存储器件中传送数据的方法。 指令被取出并解码以供处理元件执行。 基于确定指令是收集指令，处理元件确定存储器中的多个源地址，以从存储器中收集数据元素和目的地地址。 一个或多个收集的数据元素从目的地址从源地址传送到存储器中的连续位置。 基于确定该指令是散布指令，确定存储器中从邻接位置读取数据元素的源地址和存储器中的一个或多个目标地址以将数据元素存储在非连续位置的源地址，并且 数据元素被传送。

公开(公告)号：US20140130050A1

公开(公告)日：2014-05-08

申请号：US13669877

申请日：2012-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F9/46

CPC classification number: G06F9/46 ,  G06F9/3877 ,  G06F9/5044 ,  G06F2209/509 ,  Y02D10/22

Abstract: According to one embodiment of the present invention, a method for operating a computer system including a main processor, a processing element and memory is provided. The method includes receiving, at the processing element, a task from the main processor, performing, by the processing element, an instruction specified by the task, determining, by the processing element, that a function is to be executed on the main processor, the function being part of the task, sending, by the processing element, a request to the main processor for execution, the request comprising execution of the function and receiving, at the processing element, an indication that the main processor has completed execution of the function specified by the request.

Abstract translation: 根据本发明的一个实施例，提供了一种用于操作包括主处理器，处理元件和存储器的计算机系统的方法。 该方法包括在处理单元处接收来自主处理器的任务，由处理单元执行由任务指定的指令，由处理单元确定要在主处理器上执行功能， 所述功能是所述任务的一部分，由所述处理元件发送对所述主处理器执行的请求，所述请求包括所述功能的执行，并且在所述处理元件处接收到所述主处理器已完成所述主处理器的执行的指示 函数由请求指定。