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公开(公告)号：US20160344427A1
公开(公告)日：2016-11-24
申请号：US15226160
申请日：2016-08-02
Applicant: International Business Machines Corporation
Inventor： John K. DeBrosse , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Rona Yaari
CPC classification number: H03M13/353 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G11C11/4076 , G11C29/52 , G11C2029/0411 , H03M13/09
Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition, where the write-back indicator is a discrete signal sent to a memory controller, and the at least one non-volatile memory device asserting the write-back indicator extends cycle timing monitored by the memory controller while the write-back indicator is asserted. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.
Abstract translation: 根据一个方面，一种用于存储器系统中的自适应纠错的方法包括从存储器系统中的非易失性存储器件的存储器阵列中读取数据。 错误校正逻辑检查存储在存储器阵列中的至少一个错误条件的数据。 基于确定存在至少一个错误条件，由错误校正逻辑确定回写指示符以请求校正至少一个错误状态，其中写回指示符是发送到存储器控制器的离散信号 ，并且断言回写指示器的至少一个非易失性存储器件延伸由存储器控制器监视的周期定时，而写回指示器被断言。 基于确定至少一个错误条件不存在，存储器阵列的访问继续而不断言回写指示符。
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公开(公告)号：US09471422B2
公开(公告)日：2016-10-18
申请号：US14834469
申请日：2015-08-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： John K. DeBrosse , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Rona Yaari
IPC: G06F11/10 , G11C29/52 , H03M13/35 , G11C11/4076 , G11C29/04
CPC classification number: H03M13/353 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G11C11/4076 , G11C29/52 , G11C2029/0411 , H03M13/09
Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.
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43.发明申请公开(公告)号：US20160224412A1
公开(公告)日：2016-08-04
申请号：US14611351
申请日：2015-02-02
Applicant: International Business Machines Corporation
Inventor： Michael B. Healy , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule
CPC classification number: G06F11/1044 , G06F3/0619 , G06F3/064 , G06F3/0653 , G06F3/0673 , G06F11/0727 , G06F11/076 , G06F11/0766 , G06F11/0772 , G06F11/0793 , G06F11/1008 , G06F11/1024 , G06F11/1048 , H03M13/1515 , H03M13/19
Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.
Abstract translation: 本公开的实施例提供了一种用于监视具有嵌入式纠错码（ECC）的动态随机存取存储器（DRAM）装置的健康状况和预测故障的方法。 额外的寄存器被嵌入到DRAM器件中以存储关于DRAM的信息，例如由器件检测到的软错误的数量和位置。 当DRAM设备检测到软错误时，它将更新存储在附加寄存器中的信息。 控制器将存储在附加寄存器中的信息与相关联的阈值进行比较。 在一些实施例中，在将信息与相关联的阈值进行比较之后，控制器可以确定是否安排修复动作。 在其他实施例中，控制器可以确定是否警告存储器控制器DRAM可能发生故障。
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公开(公告)号：US20160180900A1
公开(公告)日：2016-06-23
申请号：US14696192
申请日：2015-04-24
Applicant: International Business Machines Corporation
Inventor： Charles A. Kilmer , Anil B. Lingambudi , Warren E. Maule , Diyanesh Babu C. Vidyapoornachary
IPC: G11C7/10
CPC classification number: G11C7/103 , G06F13/1668 , G11C11/408
Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.
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公开(公告)号：US20160034350A1
公开(公告)日：2016-02-04
申请号：US14834469
申请日：2015-08-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： John K. DeBrosse , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Rona Yaari
CPC classification number: H03M13/353 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G11C11/4076 , G11C29/52 , G11C2029/0411 , H03M13/09
Abstract: According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator.
Abstract translation: 根据一个方面，一种用于存储器系统中的自适应纠错的方法包括从存储器系统中的非易失性存储器件的存储器阵列中读取数据。 错误校正逻辑检查存储在存储器阵列中的至少一个错误条件的数据。 基于确定存在至少一个错误条件，错误校正逻辑确定回写指示符以请求校正至少一个错误状况。 基于确定至少一个错误条件不存在，存储器阵列的访问继续而不断言回写指示符。
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Patent Agency Ranking
公开(公告)号：US09146883B2
公开(公告)日：2015-09-29
申请号：US13792720
申请日：2013-03-11
Applicant: International Business Machines Corporation
Inventor： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Warren E. Maule
CPC classification number: G06F12/16 , G06F12/1483 , G06F21/00 , G06F21/62 , G06F2221/2143
Abstract: A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device.
Abstract translation: 存储器件可以配备快速擦除功能以保护存储器件的内容。 快速擦除功能可以在发出命令时立即有效地永久地禁止存储在存储设备中的数据，使得写入存储器设备的所有以前的数据不可读。 快速擦除功能可以允许使用存储器件进行新的写入操作，并且一旦接收和执行擦除命令就立即读取新写入的数据。 快速擦除功能可以开始不新写的数据的物理擦除过程，而不会改变快速擦除的其他方面。 方面可以用存储器件中的每行一个或多个比特来完成。
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公开(公告)号：US20150109874A1
公开(公告)日：2015-04-23
申请号：US14060665
申请日：2013-10-23
Applicant: International Business Machines Corporation
Inventor： Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule
IPC: G11C11/408
CPC classification number: G11C11/408 , G11C11/4087 , G11C11/4097
Abstract: A method, system and memory controller are provided for implementing memory devices with sub-bank architecture in a computer system. An array is divided into sub-blocks having odd bit lines and even bit lines. The sub-blocks are alternated with rows of sense amplifiers; wherein a particular row of sense amplifiers connects only to odd bit lines and a next row of sense amplifiers connects only to even bit lines. More than one word line for a sub-block is allowed to be active at the same time, where a first active word line will select memory cells connected to even bit lines and a second active word line will select memory cells connected to odd bit lines.
Abstract translation: 提供了一种用于在计算机系统中实现具有子银行架构的存储器件的方法，系统和存储器控制器。 阵列被划分为具有奇数位线和偶数位线的子块。 子块与行放大器交替; 其中一行读出放大器仅连接到奇数位线，而下一行读出放大器仅连接到偶数位线。 允许一个子块的多个字线同时处于活动状态，其中第一个活动字线将选择连接到偶数位线的存储单元，而第二个活动字线将选择连接到奇数位线的存储单元 。
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公开(公告)号：US20140223120A1
公开(公告)日：2014-08-07
申请号：US13758442
申请日：2013-02-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Michele M. Franceschini , Hillery C. Hunter , Ashish Jagmohan , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Warren E. Maule
IPC: G06F12/16
CPC classification number: G06F12/16 , G06F12/1483 , G06F21/00 , G06F21/62 , G06F2221/2143
Abstract: A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable. The quick erase capability may allow use of the memory device for new write operations and for reading the newly written data immediately once the erase command is received and executed. The quick erase capability may begin a physical erase process of data not newly written without altering other aspects of the quick erase. Aspects may be accomplished with one or more bits per row in a memory device.
Abstract translation: 存储器件可以配备快速擦除功能以保护存储器件的内容。 快速擦除功能可以在发出命令时立即有效地永久地禁止存储在存储设备中的数据，使得写入存储器设备的所有以前的数据不可读。 快速擦除功能可以允许使用存储器件进行新的写入操作，并且一旦接收和执行擦除命令就立即读取新写入的数据。 快速擦除功能可以开始不新写的数据的物理擦除过程，而不会改变快速擦除的其他方面。 方面可以用存储器件中的每行一个或多个比特来完成。
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公开(公告)号：US20140115281A1
公开(公告)日：2014-04-24
申请号：US13657058
申请日：2012-10-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Paul W. Coteus , Shawn A. Hall , Hillery C. Hunter , Douglas J. Joseph , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Todd E. Takken
CPC classification number: G06F3/0671 , G06F1/20 , G06F1/3275 , Y02D10/14
Abstract: According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.
Abstract translation: 根据一个实施例，存储器系统包括电路卡和电路卡上的可分离区域阵列连接器。 该系统还包括位于电路卡上的存储器件，其中存储器件被配置为经由区域阵列连接器与计算机系统的主处理器进行通信。
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公开(公告)号：US11593196B2
公开(公告)日：2023-02-28
申请号：US17539813
申请日：2021-12-01
Applicant: International Business Machines Corporation
Inventor： Kevin M. Mcilvain , Warren E. Maule , Stephen Glancy , Kyu-hyoun Kim , Edgar R. Cordero
Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.
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