公开(公告)号：US10388577B1

公开(公告)日：2019-08-20

申请号：US15938522

申请日：2018-03-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/321 ,  H01L27/12 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L21/84 ,  H01L21/3213

Abstract: A technique relates to a semiconductor device. A first work function metal is in first stack and second stacks, each having nanowires separated by the first work function metal. A mask is on the first stack such that the first work function metal in the first stack is protected while the first work function metal in the second stack is exposed. The mask is undercut by removing a portion of first work function metal in first stack, leaving a gap. A plug is formed in the gap underneath the mask so as to protect the first work function metal in first stack. First work function metal in the second stack is removed, thereby removing the first work function metal from in between the nanowires of the second stack. The mask and plug are removed from first stack. A second work function metal is formed on first and second stacks.

公开(公告)号：US10374091B2

公开(公告)日：2019-08-06

申请号：US16112841

申请日：2018-08-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Xin Miao

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: A method for forming a semiconductor structure includes forming at least one fin on a semiconductor substrate. The least one fin includes a semiconducting material. A gate is formed over and in contact with the at least one fin. A germanium comprising layer is formed over and in contact with the at least one fin. Germanium from the germanium comprising layer is diffused into the semiconducting material of the at least one fin.

公开(公告)号：US10374073B2

公开(公告)日：2019-08-06

申请号：US15623877

申请日：2017-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/423 ,  H01L29/12 ,  H01L29/06 ,  H01L29/10

Abstract: Transistors and methods of forming the same include forming a fin that has an active layer between two sacrificial layers. Material from the two sacrificial layers is etched away in a region of the fin. A gate stack is formed around the active layer in the region. Source and drain regions are formed in contact with the active layer.

公开(公告)号：US20190237541A1

公开(公告)日：2019-08-01

申请号：US16375218

申请日：2019-04-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/10

Abstract: Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Spacers are formed, with at least one top pair of spacers being positioned above an uppermost channel layer. The top pair of spacers each has a curved lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack.

公开(公告)号：US10347765B2

公开(公告)日：2019-07-09

申请号：US15847169

申请日：2017-12-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Xin Miao ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/308 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/08 ,  H01L29/51 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/36

Abstract: A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may further include forming a split fin structure from the substrate. The metal nitride is positioned in the split portion of the fin structure. The method may continue with removing the metal nitride from a source region and drain region portion of the split fin structure, in which the metal nitride remains in a channel region portion of the split fin structure. A gate structure may then be formed on a channel region portion of the fin structure. A back bias is applied to the semiconductor device using the metal nitride in the split portion of the fin structure as an electrode.

公开(公告)号：US20190198399A1

公开(公告)日：2019-06-27

申请号：US15853769

申请日：2017-12-23

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Kangguo Cheng ,  Chen Zhang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49 ,  H01L27/088 ,  H01L29/423

Abstract: Techniques for forming VFETs with differing gate lengths Lg on the same wafer using a gas cluster ion beam (GCIB) process to produce fins of differing heights are provided. In one aspect, a method of forming fins having different heights includes: patterning the fins having a uniform height in a substrate, the fins including at least one first fin and at least one second fin; forming an oxide at a base of the at least one second fin using a low-temperature directional oxidation process (e.g., GCIB oxidation); and removing the oxide from the base of the at least one second fin to reveal the at least one first fin having a height HI and the at least one second fin having a height H2, wherein H2>H1. VFETs and methods for forming VFETs having different fin heights using this process are also provided.

公开(公告)号：US20190189790A1

公开(公告)日：2019-06-20

申请号：US16271069

申请日：2019-02-08

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/7613 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.

公开(公告)号：US10325995B2

公开(公告)日：2019-06-18

申请号：US16128698

申请日：2018-09-12

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/78 ,  H01L29/40

Abstract: Provided herewith are embodiments related to a semiconductor structure and a method for forming the semiconductor structure. A first spacer layer and a second spacer layer are formed opposite a major surface of a substrate. The second spacer layer is removed using the first spacer layer as a stop layer. The removal of the second spacer layer forms an air-gap spacer in an area previously occupied by the second spacer layer.

公开(公告)号：US20190157267A1

公开(公告)日：2019-05-23

申请号：US16256443

申请日：2019-01-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02

Abstract: A method of forming features of a finFET structure includes forming fins on a surface of a substrate. A first liner is formed around each fin and a shallow trench isolation region is formed around each fin. A dopant layer is implanted in each fin. A portion of the shallow trench isolation region is etched from each fin. A first portion of the structure is blocked and the first liner replaced with a second liner in a second portion of the structure.

公开(公告)号：US10297688B2

公开(公告)日：2019-05-21

申请号：US15966232

申请日：2018-04-30

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Philip J. Oldiges ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06

Abstract: Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes forming a semiconductor fin on a source/drain region, forming a liner including a first dielectric material along sidewalls of the semiconductor fin and along sidewalls of the source/drain region, forming a second dielectric material along sidewalls of the liner including the first dielectric material, and removing the liner including the first dielectric material from sidewalls of the semiconductor fin. Removing the liner including the first dielectric material includes exposing portions of the source/drain region. The method further includes forming a spacer layer on the second dielectric material and portions of the source/drain region exposed by removing the liner including the first dielectric material and forming a gate material on the spacer layer.