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公开(公告)号：US09685499B1
公开(公告)日：2017-06-20
申请号：US15271745
申请日：2016-09-21
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Zhenxing Bi , Kangguo Cheng , Dongbing Shao , Zheng Xu
Abstract: A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact is arranged on a basal end of the second electrode.
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公开(公告)号：US09218903B2
公开(公告)日：2015-12-22
申请号：US14037415
申请日：2013-09-26
Applicant: International Business Machines Corporation
Inventor： Pinping Sun , Chengwen Pei , Zheng Xu
CPC classification number: H01F27/362 , H01F17/0013 , H01F27/2804 , H01F27/2871 , H01F27/289 , H01F41/041 , H01F2017/008 , H01F2027/2809 , H01L23/60 , H01L23/645 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure. A second ground shielding structure located within the second metal layer is electrically isolated from and circumferentially bounds the second inductor structure, whereby the first and second inductor generate a first inductance value based on the first ground shielding structure and second ground shielding structure being coupled to ground, and the first and second inductor generate a second inductance value based on the first ground shielding structure and second ground shielding structure electrically floating.
Abstract translation: 形成在半导体结构内的可重构多叠层电感器可以包括位于半导体结构的第一金属层内的第一电感结构，位于第一金属层内的第一接地屏蔽结构，其与第一电感器 结构，以及位于半导体结构的第二金属层内的第二电感结构，由此第二电感结构电耦合到第一电感结构。 位于第二金属层内的第二接地屏蔽结构与第二电感器结构电隔离并在周向上限定第二电感结构，由此第一和第二电感器基于第一接地屏蔽结构产生第一电感值，并且第二接地屏蔽结构耦合到地 并且第一和第二电感器基于第一接地屏蔽结构和电浮置的第二接地屏蔽结构产生第二电感值。
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公开(公告)号：US11311224B2
公开(公告)日：2022-04-26
申请号：US16738040
申请日：2020-01-09
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Qianwen Chen , Huan Hu , Zheng Xu , Xin Zhang
Abstract: A method is presented for forming a nanowire electrode. The method includes forming a plurality of nanowires over a first substrate, depositing a conducting layer over the plurality of nanowires, forming solder bumps and electrical interconnections over a second flexible substrate, and integrating nanowire electrode arrays to the second flexible substrate. The plurality of nanowires are silicon (Si) nanowires, the Si nanowires used as probes to penetrate skin of a subject to achieve electrical biopotential signals. The plurality of nanowires are formed over the first substrate by metal-assisted chemical etching.
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公开(公告)号：US11302532B2
公开(公告)日：2022-04-12
申请号：US16806261
申请日：2020-03-02
Applicant: International Business Machines Corporation
Inventor： Rasit Onur Topaloglu , Kafai Lai , Dongbing Shao , Zheng Xu
IPC: H01L23/528 , H01L21/033 , H01L21/311 , H01L21/768
Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.
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公开(公告)号：US11251267B2
公开(公告)日：2022-02-15
申请号：US16684022
申请日：2019-11-14
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Zhenxing Bi , Kangguo Cheng , Peng Xu , Zheng Xu
IPC: H01L29/08 , H01L27/088 , H01L21/8234 , H01L29/78 , H01L29/786 , H01L21/8238 , H01L27/092
Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.
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Patent Agency Ranking
公开(公告)号：US11121318B2
公开(公告)日：2021-09-14
申请号：US16776333
申请日：2020-01-29
Applicant: International Business Machines Corporation
Inventor： Dexin Kong , Kangguo Cheng , Juntao Li , Zheng Xu
Abstract: RRAM devices with tunable forming voltage are provided herein. A method of forming an RRAM device includes: depositing a first dielectric layer on a substrate; forming metal pads in the first dielectric layer; depositing a capping layer onto the first dielectric layer; forming heating elements in the capping layer in contact with the metal pads; forming an RRAM stack on the capping layer; patterning the RRAM stack into an RRAM cell(s) including a bottom electrode, a high-κ switching layer disposed on the bottom electrode, and a top electrode disposed on the high-κ switching layer; depositing a second dielectric layer over the RRAM cell(s); and forming a contact to the top electrode in the second dielectric layer. An RRAM device and a method of operating an RRAM device are also provided.
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公开(公告)号：US20210272806A1
公开(公告)日：2021-09-02
申请号：US16806261
申请日：2020-03-02
Applicant: International Business Machines Corporation
Inventor： Rasit Onur Topaloglu , Kafai Lai , Dongbing Shao , Zheng Xu
IPC: H01L21/033 , H01L21/311 , H01L21/768 , H01L23/528
Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.
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公开(公告)号：US20210234094A1
公开(公告)日：2021-07-29
申请号：US16776333
申请日：2020-01-29
Applicant: International Business Machines Corporation
Inventor： Dexin Kong , Kangguo Cheng , Juntao Li , Zheng Xu
Abstract: The present invention provides RRAM devices with tunable forming voltage. In one aspect, a method of forming an RRAM device includes: depositing a first dielectric layer on a substrate; forming metal pads in the first dielectric layer; depositing a capping layer onto the first dielectric layer; forming heating elements in the capping layer in contact with the metal pads; forming an RRAM stack on the capping layer; patterning the RRAM stack into an RRAM cell(s) including a bottom electrode, a high-κ switching layer disposed on the bottom electrode, and a top electrode disposed on the high-κ switching layer; depositing a second dielectric layer over the RRAM cell(s); and forming a contact to the top electrode in the second dielectric layer. An RRAM device and a method of operating an RRAM device are also provided.
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公开(公告)号：US10950545B2
公开(公告)日：2021-03-16
申请号：US16296502
申请日：2019-03-08
Applicant: International Business Machines Corporation
Inventor： Dongbing Shao , Chen Zhang , Zheng Xu , Tenko Yamashita
IPC: H01L23/52 , H01L23/50 , H01L27/092 , H01L27/115 , H01L23/528 , H01L21/822 , H01L21/8238 , H01L27/11551 , H01L27/11597
Abstract: A semiconductor structure includes a three-dimensional stacked transistor structure including first and second field-effect transistors of a first type at a first vertical level and third and fourth field-effect transistors of a second type at a second vertical level disposed over the first vertical level. The semiconductor structure also includes a first gate structure shared between the first and second field-effect transistors at the first vertical level, a second gate structure shared between the third and fourth field-effect transistors at the second vertical level, and a gate contact shared by the first and second gate structures. The wherein the first and second gate structures are vertically aligned with another in a layout of the three-dimensional stacked transistor structure between source drain/regions of the first, second, third and fourth field-effect transistors.
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公开(公告)号：US20210028175A1
公开(公告)日：2021-01-28
申请号：US17037972
申请日：2020-09-30
Applicant: International Business Machines Corporation
Inventor： Zhenxing Bi , Zheng Xu , Dexin Kong , Kangguo Cheng
IPC: H01L27/105 , H01L21/8229 , H01L29/06
Abstract: A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.
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