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    Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure
    41.
    发明授权
    Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure 有权
    半导体芯片采用双镶嵌线和贯穿衬底通孔（TSV）结构

    公开(公告)号：US09093503B1

    公开(公告)日：2015-07-28

    申请号：US14146788

    申请日：2014-01-03

    Applicant: International Business Machines Corporation

    Inventor： Fen Chen ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Kevin S. Petrarca ,  Anthony K. Stamper

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2224/13

    Abstract: Disclosed is a semiconductor chip having a dual damascene insulated wire and insulated through-substrate via (TSV) structure and methods of forming the chip. The methods incorporate a dual damascene technique wherein a trench and via opening are formed in dielectric layers above a substrate such that the trench is above a first via and the via opening is positioned adjacent to the first via and extends vertically from the trench and into the substrate. Dielectric spacers are formed on the sidewalls of the trench and via opening. A metal layer is deposited to form an insulated wire in the trench and an insulated TSV in the via opening. Thus, the insulated wire electrically connects the insulated TSV to the first via and, thereby to an on-chip device or lower metal level wire below. Subsequently, the substrate is thinned to expose the insulated TSV at the bottom surface of the substrate.

    Abstract translation: 公开了一种具有双镶嵌绝缘线和绝缘的穿通基板通孔（TSV）结构的半导体芯片以及形成芯片的方法。 所述方法包括双镶嵌技术，其中沟槽和通孔开口形成在衬底上方的电介质层中，使得沟槽位于第一通孔上方，并且通孔开口定位成与第一通孔相邻并且从沟槽垂直延伸并进入 基质。 电介质间隔物形成在沟槽和通孔开口的侧壁上。 沉积金属层以在沟槽中形成绝缘电线，并在通孔开口中形成绝缘的TSV。 因此，绝缘线将绝缘TSV与第一通孔电连接，从而将其连接到下面的片上器件或下部金属级线。 随后，将衬底变薄以暴露衬底底部的绝缘TSV。

    Interdigitated capacitors with a zero quadratic voltage coefficient of capacitance or zero linear temperature coefficient of capacitance
    43.
    发明授权
    Interdigitated capacitors with a zero quadratic voltage coefficient of capacitance or zero linear temperature coefficient of capacitance 有权
    具有零二次电容系数或零线性温度系数电容的交错电容器

    公开(公告)号：US08901710B2

    公开(公告)日：2014-12-02

    申请号：US13778321

    申请日：2013-02-27

    Applicant: International Business Machines Corporation

    Inventor： Frederick G. Anderson ,  Natalie B Feilchenfeld ,  Zhong-Xiang He ,  Theodore J. Letavic ,  Yves T. Ngu

    IPC: H01L21/20 ,  H01L49/02

    CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (Tcc) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (Vcc2) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.

    Abstract translation: 公开了一种叉指电容器和交叉指向的垂直原始电容器，每个电容器相对于特定参数具有相对较低（例如，零）的电容系数。 例如，电容器可以具有零线性电容温度系数（Tcc），以将电容变化限制为温度或零净二次电压电容系数（Vcc2），以将电容变化限制为电压的函数。 在任何情况下，由于所使用的介电材料的类型及其各自的厚度，每个电容器可以结合至少两个不同的平板电介质，其具有与特定参数相反的极性电容系数。 结果，不同的电介质板将对彼此抵消的电容器的电容产生相反的影响，使得电容器相对于特定参数具有零净电容系数。

    Back-end-of-line metal-oxide-semiconductor varactors
    45.
    发明授权
    Back-end-of-line metal-oxide-semiconductor varactors 有权
    后端金属氧化物半导体变容二极管

    公开(公告)号：US08809155B2

    公开(公告)日：2014-08-19

    申请号：US13644918

    申请日：2012-10-04

    Applicant: International Business Machines Corporation

    Inventor： John J. Ellis-Monaghan ,  Michael J. Hauser ,  Zhong-Xiang He ,  Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Anthony K. Stamper

    IPC: H01L21/336

    CPC classification number: H01L29/93 ,  H01L27/0688 ,  H01L27/0808

    Abstract: Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator.

    Abstract translation: 变容二极管的器件结构，设计结构和制造方法。 器件结构包括形成在电介质层上的第一电极和形成在第一电极上的半导体本体。 半导体本体由非晶态或多晶态的含硅半导体材料构成。 器件结构还包括形成在半导体主体上的电极绝缘体和形成在电极绝缘体上的第二电极。

    METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY
    47.
    发明申请
    METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY 有权
    选择性反向掩模平面化和互连结构的方法

    公开(公告)号：US20140131893A1

    公开(公告)日：2014-05-15

    申请号：US14158904

    申请日：2014-01-20

    Applicant: International Business Machines Corporation

    Inventor： Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC: H01L23/528

    CPC classification number: H01L23/528 ,  H01L21/31056 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

    Abstract translation: 用于平坦化诸如电介质的材料层的平面化方法以及通过平面化方法形成的互连结构。 该方法包括在多个导电特征的顶表面和导电特征之间的衬底的顶表面上沉积第一介电层。 第一介电层的一部分从至少一个导电特征的顶表面选择性地去除，而不去除导电特征之间的第一介电层的一部分。 第二电介质层形成在至少一个导电特征的顶表面上和第一介电层的顶表面上，并且第二介电层的顶表面被平坦化。 作为蚀刻停止件操作的层位于导电特征中的至少一个的顶表面和第二介电层之间。

    Isolated wire structures with reduced stress, methods of manufacturing and design structures
    48.
    发明授权
    Isolated wire structures with reduced stress, methods of manufacturing and design structures 失效
    具有减小应力的隔离线结构，制造方法和设计结构

    公开(公告)号：US08659173B1

    公开(公告)日：2014-02-25

    申请号：US13734130

    申请日：2013-01-04

    Applicant: International Business Machines Corporation

    Inventor： Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee

    IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC classification number: H01L21/32139 ,  H01L21/28 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5227 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit (IC) including a set of isolated wire structures disposed within a layer of the IC, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween. The method further includes forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures. The method further includes forming a photosensitive material over the capping layer. The method further includes forming an opening in the photosensitive material between the adjacent wiring structures to expose the capping layer. The method further includes removing the exposed capping layer.

    Abstract translation: 公开了一种集成电路（IC），其包括设置在IC层内的一组隔离线结构，其制造方法和设计结构。 该方法包括在相同水平上形成相邻的布线结构，其间具有空间。 该方法还包括在相同级别的相邻布线结构上形成覆盖层，包括在相邻布线结构之间的材料的表面上。 该方法还包括在覆盖层上形成感光材料。 该方法还包括在相邻布线结构之间的感光材料中形成一个开口以露出封盖层。 该方法还包括去除暴露的盖层。

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