公开(公告)号：US07009273B2

公开(公告)日：2006-03-07

申请号：US10665614

申请日：2003-09-19

申请人： Kazumi Inoh ,  Hidemi Ishiuchi ,  Satoshi Matsuda ,  Ichiro Mizushima ,  Tsutomu Sato

发明人： Kazumi Inoh ,  Hidemi Ishiuchi ,  Satoshi Matsuda ,  Ichiro Mizushima ,  Tsutomu Sato

IPC分类号： H01L29/00

CPC分类号： H01L27/10894 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/84 ,  H01L27/0218 ,  H01L27/105 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10885 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/7841

摘要： A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.

公开(公告)号：US20050019999A1

公开(公告)日：2005-01-27

申请号：US10921273

申请日：2004-08-19

申请人： Takashi Yamada ,  Hajime Nagano ,  Ichiro Mizushima ,  Tsutomu Sato ,  Hisato Oyamatsu ,  Shinichi Nitta

发明人： Takashi Yamada ,  Hajime Nagano ,  Ichiro Mizushima ,  Tsutomu Sato ,  Hisato Oyamatsu ,  Shinichi Nitta

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/108 ,  H01L27/12 ,  H01L21/336 ,  H01L21/76 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/10894 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

摘要翻译： 半导体芯片包括基底基板，在基底基板的一部分上具有体积生长层的体器件区域，在基底基板上具有掩埋绝缘体的SOI器件区域和埋入绝缘体上的硅层，以及边界层 位于体器件区域和SOI器件区域之间的边界处。 本体装置区域具有第一装置制造表面，其中大块装置位于本体生长层上。 SOI器件区域具有第二器件制造表面，其中SOI器件位于硅层上。 第一和第二装置制造表面被定位在基本均匀的水平。

公开(公告)号：US06600189B1

公开(公告)日：2003-07-29

申请号：US09598379

申请日：2000-06-21

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Junichiro Iba

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Junichiro Iba

IPC分类号： H01L27108

CPC分类号： H01L27/1087 ,  H01L28/84 ,  Y10S438/909

摘要： A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.

摘要翻译： 半导体器件包括在其表面上具有沟槽的半导体衬底和嵌入沟槽内部的嵌入构件。 虽然当垂直于沟槽深度方向的第一平面切割沟槽的部分被定义为第一部分，并且当垂直于沟槽深度方向的第二平面切割沟槽的部分时 并且比所述第一平面更靠近所述沟槽的底部被限定为第二部分，所述第一部分的面积小于所述第二部分的面积，并且所述第一部分的最小曲率半径小于所述第一部分的最小半径 第二部分的曲率。 结果，可以减小进入沟槽底部的电场的浓度。

公开(公告)号：US06570217B1

公开(公告)日：2003-05-27

申请号：US09296669

申请日：1999-04-22

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

IPC分类号： H01L2926

CPC分类号： H01L29/66583 ,  H01L21/324 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7831 ,  H01L29/78639

摘要： To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.

公开(公告)号：US08013398B2

公开(公告)日：2011-09-06

申请号：US12056909

申请日：2008-03-27

申请人： Shinji Mori ,  Tsutomu Sato ,  Koji Matsuo

发明人： Shinji Mori ,  Tsutomu Sato ,  Koji Matsuo

IPC分类号： H01L29/78

CPC分类号： H01L29/772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof.

摘要翻译： 半导体器件包括具有Si沟道的第一pMISFET区，具有Si沟道的第二pMISFET区和具有Si沟道的nMISFET区。 将第一压缩应变施加到Si沟道的第一SiGe层嵌入并形成在第一pMISFET区域中以夹持其Si沟道，并且将施加与第一压缩应变不同的第二压缩应变的第二SiGe层嵌入并形成 在第二pMISFET区域夹持其Si通道。

公开(公告)号：USRE45462E1

公开(公告)日：2015-04-14

申请号：US13569604

申请日：2012-08-08

申请人： Shinji Mori ,  Tsutomu Sato ,  Koji Matsuo

发明人： Shinji Mori ,  Tsutomu Sato ,  Koji Matsuo

IPC分类号： H01L29/78 ,  H01L29/772

CPC分类号： H01L29/772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof.

摘要翻译： 半导体器件包括具有Si沟道的第一pMISFET区，具有Si沟道的第二pMISFET区和具有Si沟道的nMISFET区。 将第一压缩应变施加到Si沟道的第一SiGe层嵌入并形成在第一pMISFET区域中以夹持其Si沟道，并且将施加与第一压缩应变不同的第二压缩应变的第二SiGe层嵌入并形成 在第二pMISFET区域夹持其Si通道。

公开(公告)号：US08124472B2

公开(公告)日：2012-02-28

申请号：US13205950

申请日：2011-08-09

申请人： Shinji Mori ,  Tsutomu Sato ,  Koji Matsuo

发明人： Shinji Mori ,  Tsutomu Sato ,  Koji Matsuo

IPC分类号： H01L29/78

CPC分类号： H01L29/772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof.

摘要翻译： 半导体器件包括具有Si沟道的第一pMISFET区，具有Si沟道的第二pMISFET区和具有Si沟道的nMISFET区。 将第一压缩应变施加到Si沟道的第一SiGe层嵌入并形成在第一pMISFET区域中以夹持其Si沟道，并且将施加与第一压缩应变不同的第二压缩应变的第二SiGe层嵌入并形成 在第二pMISFET区域夹持其Si通道。

公开(公告)号：US20110294271A1

公开(公告)日：2011-12-01

申请号：US13205950

申请日：2011-08-09

申请人： Shinji MORI ,  Tsutomu Sato ,  Koji Matsuo

发明人： Shinji MORI ,  Tsutomu Sato ,  Koji Matsuo

IPC分类号： H01L21/8238

CPC分类号： H01L29/772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof.

摘要翻译： 半导体器件包括具有Si沟道的第一pMISFET区，具有Si沟道的第二pMISFET区和具有Si沟道的nMISFET区。 将第一压缩应变施加到Si沟道的第一SiGe层嵌入并形成在第一pMISFET区域中以夹持其Si沟道，并且将施加与第一压缩应变不同的第二压缩应变的第二SiGe层嵌入并形成 在第二pMISFET区域夹持其Si通道。

公开(公告)号：US20080237732A1

公开(公告)日：2008-10-02

申请号：US12056909

申请日：2008-03-27

申请人： Shinji MORI ,  Tsutomu Sato ,  Koji Matsuo

发明人： Shinji MORI ,  Tsutomu Sato ,  Koji Matsuo

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof.

摘要翻译： 半导体器件包括具有Si沟道的第一pMISFET区，具有Si沟道的第二pMISFET区和具有Si沟道的nMISFET区。 将第一压缩应变施加到Si沟道的第一SiGe层嵌入并形成在第一pMISFET区域中以夹持其Si沟道，并且将施加与第一压缩应变不同的第二压缩应变的第二SiGe层嵌入并形成 在第二pMISFET区域夹持其Si通道。

公开(公告)号：US09301917B2

公开(公告)日：2016-04-05

申请号：US13824598

申请日：2011-10-14

申请人： Masanori Fukushima ,  Hiroaki Matsubara ,  Satoaki Matoba ,  Shigeki Hijikata ,  Yu Aso ,  Tsutomu Sato

发明人： Masanori Fukushima ,  Hiroaki Matsubara ,  Satoaki Matoba ,  Shigeki Hijikata ,  Yu Aso ,  Tsutomu Sato

IPC分类号： A61K38/00 ,  A61K9/00 ,  A61K31/7004 ,  A61K31/7008 ,  A61K45/06 ,  A61K38/39 ,  A61K9/51 ,  A61K47/26 ,  A61K47/42 ,  A61K38/27 ,  A61K38/18

CPC分类号： A61K9/0002 ,  A61K9/0024 ,  A61K9/5123 ,  A61K31/7004 ,  A61K31/7008 ,  A61K38/1808 ,  A61K38/1816 ,  A61K38/1825 ,  A61K38/1858 ,  A61K38/27 ,  A61K38/39 ,  A61K45/06 ,  A61K47/26 ,  A61K47/42 ,  A61K2300/00

摘要： Provided is a pharmaceutical composition, including a drug and a collagen, in which the composition is satisfactory in handleability and has sustained-release property. The sustained-release pharmaceutical composition includes: a drug; a collagen; and at least one kind of sugar selected from monosaccharides, disaccharides, trisaccharides, and tetrasaccharides. The inventors of the present invention have found that the in vivo administration of a collagen solution containing a sugar results in the gelation of a collagen. Based on this finding, the inventors have found that a composition containing a drug, a collagen, and a sugar can control the release rate of the drug, and such composition can be used as a sustained-release pharmaceutical composition.

摘要翻译： 本发明提供包含药物和胶原的药物组合物，其组合物的操作性良好且具有缓释性。 缓释药物组合物包括：药物; 胶原蛋白 和选自单糖，二糖，三糖和四糖中的至少一种糖。 本发明的发明人已经发现，含有糖的胶原溶液的体内施用导致胶原蛋白的凝胶化。 基于该发现，本发明人发现含有药物，胶原和糖的组合物可以控制药物的释放速度，并且这种组合物可以用作缓释药物组合物。