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公开(公告)号：US20210288673A1
公开(公告)日：2021-09-16
申请号：US17191924
申请日：2021-03-04
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel
Abstract: A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.
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公开(公告)号：US10951240B2
公开(公告)日：2021-03-16
申请号：US16716735
申请日：2019-12-17
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel
Abstract: A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.
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公开(公告)号：US10903859B2
公开(公告)日：2021-01-26
申请号：US16380089
申请日：2019-04-10
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel , Thomas Rabenalt
Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.
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公开(公告)号：US20200371864A1
公开(公告)日：2020-11-26
申请号：US16881473
申请日：2020-05-22
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Klaus Oberlaender , Christian Badack , Michael Goessel
Abstract: A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.
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公开(公告)号：US20200301614A1
公开(公告)日：2020-09-24
申请号：US16820784
申请日：2020-03-17
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel , Thomas Rabenalt
IPC: G06F3/06
Abstract: What is specified is a method for transforming a first binary signal read from a memory, wherein the first binary signal is transformed into a second binary signal provided that the first binary signal is a code word or a predefined code word of a k-out-of-n code, wherein the first binary signal is transformed into a predefined signal provided that the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code, wherein the predefined signal is different than the second binary signal. A corresponding device is furthermore specified.
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Patent Agency Ranking
公开(公告)号：US10514852B2
公开(公告)日：2019-12-24
申请号：US15898979
申请日：2018-02-19
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel
Abstract: A method for reading memory cells from a memory is stated, inter alia, in which physical values are determined from a number of n memory cells, wherein n is at least three, in which the physical values are at least partially compared with one another, in which K different digital memory cell values are assigned to the n memory cells on the basis of the compared physical values, and in which a code word of an n1-, . . . , nK-out-of-n code is assigned to the digital memory cell values obtained in this manner. In particular, the following apply in this case: n≥3, n1≥1 to nK≥1, K≥2 and m≥1.
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公开(公告)号：US20180240517A1
公开(公告)日：2018-08-23
申请号：US15898979
申请日：2018-02-19
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel
Abstract: A method for reading memory cells from a memory is stated, inter alia, in which physical values are determined from a number of n memory cells, wherein n is at least three, in which the physical values are at least partially compared with one another, in which K different digital memory cell values are assigned to the n memory cells on the basis of the compared physical values, and in which a code word of an n1-, . . . , nK-out-of-n code is assigned to the digital memory cell values obtained in this manner. In particular, the following apply in this case: n≥3, n1≥1 to nK≥1, K≥2 and m≥1.
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公开(公告)号：US20180052626A1
公开(公告)日：2018-02-22
申请号：US15670436
申请日：2017-08-07
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel , Albrecht Mayer
CPC classification number: G06F3/0619 , G06F11/073 , G06F11/076 , G06F11/079 , G06F11/1072 , G11C11/5628
Abstract: The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.
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公开(公告)号：US20170220417A1
公开(公告)日：2017-08-03
申请号：US15410912
申请日：2017-01-20
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Michael Goessel , Karl Hofmann
CPC classification number: G06F11/1068 , G06F11/1048 , G11C29/52 , G11C2029/0411 , H03M13/1102 , H03M13/136 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/2906 , H03M13/353 , H03M13/616
Abstract: In various embodiments, a method of correcting and/or detecting an error in a memory device is provided. The method may include, in a first operations mode, applying a first code to detect and/or correct an error, andin a second operations mode after an inactive mode and before entering the first operations mode, applying a second code for correcting and/or detecting an error, wherein the first code and the second code have different code words.
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公开(公告)号：US20170126253A1
公开(公告)日：2017-05-04
申请号：US15337286
申请日：2016-10-28
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Christian Badack , Michael Goessel
CPC classification number: H03M13/2906 , G06F11/10 , H03M13/152 , H03M13/1525 , H03M13/1545 , H03M13/1575
Abstract: A circuit arrangement for determining a correction signal on the basis of at least one bit error of a binary word is specified, including a plurality of subcircuits (ST), wherein a respective subcircuit is provided for a bit position to be corrected of the binary word, wherein each of the subcircuits provides at least two locator polynomial values, and comprising a selection unit, which determines a correction signal depending on the locator polynomial values and depending on an error signal (err, E). A method for driving such a circuit arrangement is furthermore proposed.
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