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104 条记录 (耗时 0.023 秒)

    Programmable interface to in-memory cache processor
    44.
    发明授权
    Programmable interface to in-memory cache processor 有权

    公开(公告)号：US11151046B2

    公开(公告)日：2021-10-19

    申请号：US16921685

    申请日：2020-07-06

    申请人： Intel Corporation

    发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

    IPC分类号： G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06 ,  G06F8/41 ,  G06F9/455

    摘要： The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

    VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS
    47.
    发明申请
    VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20200335610A1

    公开(公告)日：2020-10-22

    申请号：US16957667

    申请日：2018-02-28

    申请人： Intel Corporation

    发明人： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

    IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

    摘要： Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

    TRANSISTOR DEVICE WITH VARIOUSLY CONFORMAL GATE DIELECTRIC LAYERS
    48.
    发明申请
    TRANSISTOR DEVICE WITH VARIOUSLY CONFORMAL GATE DIELECTRIC LAYERS 审中-公开

    公开(公告)号：US20200312976A1

    公开(公告)日：2020-10-01

    申请号：US16363632

    申请日：2019-03-25

    申请人： Intel Corporation

    发明人： Seung Hoon Sung ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Uygar Avci ,  Devin Merrill ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Owen Loh

    IPC分类号： H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

    摘要： Techniques and mechanisms to provide electrical insulation between a gate and a channel region of a non-planar circuit device. In an embodiment, the gate structure, and insulation spacers at opposite respective sides of the gate structure, each extend over a semiconductor fin structure. In a region between the insulation spacers, a first dielectric layer extends conformally over the fin, and a second dielectric layer adjoins and extends conformally over the first dielectric layer. A third dielectric layer, adjoining the second dielectric layer and the insulation spacers, extends under the gate structure. Of the first, second and third dielectric layers, the third dielectric layer is conformal to respective sidewalls of the insulation spacers. In another embodiment, the second dielectric layer is of dielectric constant which is greater than that of the first dielectric layer, and equal to or less than that of the third dielectric layer.

    Combinatorial magneto electric spin orbit logic
    49.
    发明授权
    Combinatorial magneto electric spin orbit logic 有权

    公开(公告)号：US10749104B2

    公开(公告)日：2020-08-18

    申请号：US16217807

    申请日：2018-12-12

    申请人： Intel Corporation

    发明人： Huichu Liu ,  Daniel Morris ,  Tanay Karnik ,  Sasikanth Manipatruni ,  Kaushik Vaidyanathan ,  Ian Young

    IPC分类号： H01L43/02 ,  H03K19/18 ,  H01L27/22 ,  H01L43/10

    摘要： Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.