中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

150 records (took 0.019 seconds)

    Diffusion Barrier Layer for Resistive Random Access Memory Cells
    41.
    发明申请
    Diffusion Barrier Layer for Resistive Random Access Memory Cells 有权
    电阻随机存取存储单元的扩散阻挡层

    公开(公告)号：US20140103282A1

    公开(公告)日：2014-04-17

    申请号：US13652742

    申请日：2012-10-16

    Applicant: INTERMOLECULAR INC.

    Inventor： Yun Wang ,  Imran Hashim

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

    Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.

    Abstract translation: 提供了具有由各种材料形成的扩散阻挡层的电阻随机存取存储器（ReRAM）单元，例如氧化铍或钛硅氮化物。 在ReRAM单元中使用的电阻开关层通常需要具有至少一个惰性界面，使得基本上没有材料通过该界面。 另一个（反应式）接口可用于引入和去除导致切换的电阻式开关层的缺陷。 虽然一些电极材料（例如铂和掺杂多晶硅）可能形成惰性界面，但是这些材料通常难以整合。 为了扩大电极材料选择，扩散阻挡层设置在电极和电阻开关层之间，并与电阻式开关层形成惰性界面。 在一些实施例中，氮化钽和氮化钛可用于由这种扩散阻挡层分开的电极。

    Diffusion barrier layer for resistive random access memory cells
    42.
    发明授权
    Diffusion barrier layer for resistive random access memory cells 有权
    用于电阻随机存取存储器单元的扩散势垒层

    公开(公告)号：US08686389B1

    公开(公告)日：2014-04-01

    申请号：US13652742

    申请日：2012-10-16

    Applicant: Intermolecular Inc.

    Inventor： Yun Wang ,  Imran Hashim

    IPC: H01L29/02

    CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

    Abstract: Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.

    Abstract translation: 提供了具有由各种材料形成的扩散阻挡层的电阻随机存取存储器（ReRAM）单元，例如氧化铍或钛硅氮化物。 在ReRAM单元中使用的电阻开关层通常需要具有至少一个惰性界面，使得基本上没有材料通过该界面。 另一个（反应式）接口可用于引入和去除导致切换的电阻式开关层的缺陷。 虽然一些电极材料（例如铂和掺杂多晶硅）可能形成惰性界面，但是这些材料通常难以整合。 为了扩大电极材料选择，扩散阻挡层设置在电极和电阻开关层之间，并与电阻式开关层形成惰性界面。 在一些实施例中，氮化钽和氮化钛可用于由这种扩散阻挡层分开的电极。

    Work Function Tailoring for Nonvolatile Memory Applications
    43.
    发明申请
    Work Function Tailoring for Nonvolatile Memory Applications 审中-公开
    非易失性存储器应用的工作功能定制

    公开(公告)号：US20140065790A1

    公开(公告)日：2014-03-06

    申请号：US14078838

    申请日：2013-11-13

    Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

    Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

    IPC: H01L45/00

    CPC classification number: H01L45/1608 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/065 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1641

    Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

    Abstract translation: 本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。 在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成 器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

    High Throughput Current-Voltage Combinatorial Characterization Tool and Method for Combinatorial Solar Test Substrates
    44.
    发明申请
    High Throughput Current-Voltage Combinatorial Characterization Tool and Method for Combinatorial Solar Test Substrates 审中-公开

    公开(公告)号：US20130342230A1

    公开(公告)日：2013-12-26

    申请号：US13971325

    申请日：2013-08-20

    Applicant: Intermolecular, Inc

    Inventor： Yun Wang ,  Tony P. Chiang ,  Chi-I Lang

    IPC: G01R31/26

    CPC classification number: G01R31/26 ,  G01N21/55 ,  G01R31/2607 ,  H02S50/10

    Abstract: Measuring current-voltage (I-V) characteristics of a solar cell using a lamp that emits light, a substrate that includes a plurality of solar cells, a positive electrode attached to the solar cells, and a negative electrode peripherally deposited around each of the solar cells and connected to a common ground, an articulation platform coupled to the substrate, a multi-probe switching matrix or a Z-stage device, a programmable switch box coupled to the multi-probe switching matrix or Z-stage device and selectively articulating the probes by raising the probes until in contact with at least one of the positive electrode and the negative electrode and lowering the probes until contact is lost with at least one of the positive electrode and the negative electrode, a source meter coupled to the programmable switch box and measuring the I-V characteristics of the substrate.

    Atomic Layer Deposition of Hafnium and Zirconium Oxides for Memory Applications
    45.
    发明申请
    Atomic Layer Deposition of Hafnium and Zirconium Oxides for Memory Applications 审中-公开
    用于记忆应用的铪和氧化锆的原子层沉积

    公开(公告)号：US20130334484A1

    公开(公告)日：2013-12-19

    申请号：US13972587

    申请日：2013-08-21

    Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

    Inventor： Yun Wang ,  Tony P. Chiang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616

    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.

    Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其具有设置在金属氧化物本体层上或其上的金属氧化物缓冲层。 金属氧化物本体层含有富金属氧化物材料，金属氧化物缓冲层含有贫金属氧化物。 由于金属氧化物本体层比金属氧化物缓冲层氧化较少或更金属，所以金属氧化物本体层的电阻小于金属氧化物缓冲层的电阻。 在一个实例中，金属氧化物本体层含有富金属氧化铪材料，金属氧化物缓冲层含有贫金属氧化锆材料。

    Memory Cell Having an Integrated Two-Terminal Current Limiting Resistor
    47.
    发明申请
    Memory Cell Having an Integrated Two-Terminal Current Limiting Resistor 有权
    具有集成两端限流电阻的存储单元

    公开(公告)号：US20130221315A1

    公开(公告)日：2013-08-29

    申请号：US13721310

    申请日：2012-12-20

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

    IPC: H01L45/00

    CPC classification number: H01L45/12 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    Abstract: A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

    Abstract translation: 提供了一种结合到具有改进的性能和寿命的电阻式开关存储单元中的电阻器结构。 电阻器结构可以是设计成减小流过存储器单元的最大电流的两端结构。 还提供了一种用于制造这种存储单元的方法。 该方法包括沉积电阻器结构并沉积存储单元的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联布置以限制存储单元的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器单元的开关规范的期望的开关电流水平是非常有用的。 存储单元可以形成为可用于各种电子设备的大容量非易失性存储器集成电路的一部分。

    Doped oxide dielectrics for resistive random access memory cells
    49.
    发明授权
    Doped oxide dielectrics for resistive random access memory cells 有权
    用于电阻随机存取存储器单元的掺杂氧化物电介质

    公开(公告)号：US09425394B2

    公开(公告)日：2016-08-23

    申请号：US14565712

    申请日：2014-12-10

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Brian Butcher ,  Randall J. Higuchi ,  Yun Wang

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1616 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

    Abstract: Provided are methods of fabricating memory cells such as resistive random access memory (ReRAM) cells. A method involves forming a first layer including two high-k dielectric materials such that one material has a higher dielectric constant than the other material. In some embodiments, hafnium oxide and titanium oxide form the first layer. The higher-k material may be present at a lower concentration. In some embodiments, a concentration ratio of these two high-k materials is between about 3 and 7. The first layer may be formed using atomic layer deposition. The first layer is then annealed in an oxygen-containing environment. The method may proceed with forming a second layer including a low-k dielectric material, such as silicon oxide, and forming an electrode. After forming the electrode, the memory cell is annealed in a nitrogen containing environment. The nitrogen anneal may be performed at a higher temperature than the oxygen anneal.

    Abstract translation: 提供制造诸如电阻随机存取存储器（ReRAM）单元的存储单元的方法。 一种方法包括形成包括两个高k介电材料的第一层，使得一种材料具有比其它材料更高的介电常数。 在一些实施方案中，氧化铪和氧化钛形成第一层。 较高k的材料可以以更低的浓度存在。 在一些实施方案中，这两种高k材料的浓度比在约3和7之间。第一层可以使用原子层沉积形成。 然后将第一层在含氧环境中退火。 该方法可以继续形成包括低k介电材料（例如氧化硅）的第二层，并形成电极。 在形成电极之后，在含氮环境中对存储单元进行退火。 氮退火可以在比氧退火更高的温度下进行。

    Doped Ternary Nitride Embedded Resistors for Resistive Random Access Memory Cells
    50.
    发明申请
    Doped Ternary Nitride Embedded Resistors for Resistive Random Access Memory Cells 有权
    用于电阻随机存取存储单元的掺杂三元氮化物嵌入式电阻器

    公开(公告)号：US20160163977A1

    公开(公告)日：2016-06-09

    申请号：US14562971

    申请日：2014-12-08

    Applicant: Intermolecular Inc.

    Inventor： Yun Wang

    IPC: H01L45/00

    CPC classification number: H01L45/1233 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/145 ,  H01L45/1608 ,  H01L45/1641

    Abstract: Provided are resistive random access memory (ReRAM) cells with embedded resistors and methods of fabricating these cells. An embedded resistor may include a metal silicon nitride of a first metal and may be doped with a second metal, which is different from the first metal. The second metal may have less affinity to form covalent bonds with nitrogen than the first metal. As such, the second metal may be unbound and more mobile in the embedded resistor that the first metal. The second metal may help establishing conductive paths in the embedded resistor in addition to the metal nitride resulting in more a stable resistivity despite changing potential applies to the ReRAM cell. In other words, the embedded resistor having such composition will have more linear I-V performance. The concentration of the second metal in the embedded resistor may be substantially less than the concentration of the first metal.

    Abstract translation: 提供了具有嵌入电阻器的电阻随机存取存储器（ReRAM）单元和制造这些单元的方法。 嵌入式电阻器可以包括第一金属的金属氮化硅，并且可以掺杂有与第一金属不同的第二金属。 与第一种金属相比，第二种金属可能具有较小的亲和力以形成与氮的共价键。 因此，第二金属可以是未绑定的，并且在嵌入式电阻器中移动更多的是第一金属。 除了金属氮化物之外，第二种金属可能有助于在嵌入式电阻器中建立导电路径，导致更多的稳定电阻率，尽管对ReRAM电池的应用有变化。 换句话说，具有这种组成的嵌入式电阻器将具有更多的线性I-V性能。 嵌入式电阻器中的第二金属的浓度可以显着小于第一金属的浓度。

Patent Agency Ranking