公开(公告)号：US5648934A

公开(公告)日：1997-07-15

申请号：US596528

申请日：1996-02-05

申请人： James E. O'Toole

发明人： James E. O'Toole

IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C29/44 ,  G11C29/52

CPC分类号： G11C29/765 ,  G11C29/04 ,  G11C29/44 ,  G11C29/52 ,  G11C29/82

摘要： A programmable non-volatile memory device includes a memory array of addressable memory cells and multiple redundant memory cells for replacing defective memory cells in the memory array. To program the memory device, data is written to one or more of the addressable memory cells in the memory array. In the event that the data is not validly written into the address memory cells, repeated attempts are made to program the same memory cells. The memory device includes a counter for counting the number of times the same memory cells are accessed for programming purposes. When a predetermined number of such programming cycles is achieved, the address memory cells are determined to be defective. A redundancy address matching circuit is enabled at this point to replace the defective memory cells with redundant memory cells that can be validly programmed. The memory device subsequently routes the data to the redundant memory cells instead of the defective memory cells. A system including a programming machine and the programmable non-volatile memory device, and methods for programming such memory devices, are also disclosed.

摘要翻译： 可编程非易失性存储器件包括可寻址存储器单元的存储器阵列和用于替换存储器阵列中的有缺陷的存储器单元的多个冗余存储器单元。 为了对存储器件进行编程，将数据写入存储器阵列中的一个或多个可寻址存储单元。 在数据未被有效地写入地址存储单元的情况下，重复尝试对相同的存储单元进行编程。 存储器件包括用于计数用于编程目的的相同存储器单元被访问次数的计数器。 当达到预定数量的这种编程周期时，确定地址存储单元是有缺陷的。 此时，冗余地址匹配电路被使能以用有效编程的冗余存储器单元替换有缺陷的存储单元。 存储器件随后将数据路由到冗余存储器单元而不是有缺陷的存储器单元。 还公开了一种包括编程机和可编程非易失性存储器件的系统，以及用于编程这种存储器件的方法。

公开(公告)号：US4338679A

公开(公告)日：1982-07-06

申请号：US273845

申请日：1980-12-24

申请人： James E. O'Toole

发明人： James E. O'Toole

IPC分类号： G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/40

CPC分类号： G11C8/18 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10

摘要： A circuit (10) is disclosed for use in a semiconductor integrated circuit memory. The integrated circuit memory includes row lines (102-108) which serve to activate the access transistors for memory cells (102a-108a) within the memory circuit. A row decoder circuit (36) receives a plurality of first address bits and produces a drive signal output when the decoder circuit is selected. A transition detector circuit (24) produces a transition signal whenever the state of any of the address bits is changed. A clock decoder circuit receives a plurality of second address bits together with the transition signal to produce a selected clock signal (.phi..sub.A -.phi..sub.D). The combination of the transition signal and the output of the row decoder circuit (36) serves to precharge the gate terminals of the row driver transistors (80-86) for the row lines (102-108). The selected row line receives the active state of the clock signal (.phi..sub.A -.phi..sub.D) which causes the gate terminal of the selected row driver transistor to be capacitively coupled to a higher voltage than the clock signal to therefore supply the full clock signal voltage to the row line (102-108). The voltage on the row line then activates the access transistors (118, 120) for the memory cells (106a) on the row line (106). This enables a maximum charge to be stored in or read from the memory cell (106a).

摘要翻译： PCT No.PCT / US80 / 01727 Sec。 371日期1980年12月24日第 102（e）1980年12月24日的PCT日期为1980年12月24日提交。公开了一种用于半导体集成电路存储器的电路（10）。 集成电路存储器包括用于激活存储器电路内的存储器单元（102a-108a）的存取晶体管的行线（102-108）。 行解码器电路（36）接收多个第一地址位并在选择解码器电路时产生驱动信号输出。 只要任何地址位的状态改变，转换检测器电路（24）产生转换信号。 时钟解码器电路与转换信号一起接收多个第二地址位以产生所选择的时钟信号（phi-A-phi D）。 转换信号和行解码器电路（36）的输出的组合用于对行线（102-108）的行驱动器晶体管（80-86）的栅极端子进行预充电。 所选择的行线接收时钟信号（phi-phi D）的有效状态，使得所选行驱动晶体管的栅极端子电容耦合到比时钟信号更高的电压，从而提供全时钟信号电压 到行行（102-108）。 然后，行线上的电压然后激活用于行线（106）上的存储单元（106a）的存取晶体管（118,120）。 这使得能够将最大电荷存储在存储单元（106a）中或从存储单元读取。

公开(公告)号：US5513144A

公开(公告)日：1996-04-30

申请号：US387244

申请日：1995-02-13

申请人： James E. O'Toole

发明人： James E. O'Toole

IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C29/44 ,  G11C29/52

CPC分类号： G11C29/765 ,  G11C29/04 ,  G11C29/44 ,  G11C29/52 ,  G11C29/82

摘要： A programmable non-volatile memory device includes a memory array of addressable memory cells and multiple redundant memory cells for replacing defective memory cells in the memory array. To program the memory device, data is written to one or more of the addressable memory cells in the memory array. In the event that the data is not validly written into the address memory cells, repeated attempts are made to program the same memory cells. The memory device includes a counter for counting the number of times the same memory cells are accessed for programming purposes. When a predetermined number of such programming cycles is achieved, the address memory cells are determined to be defective. A redundancy address matching circuit is enabled at this point to replace the defective memory cells with redundant memory cells that can be validly programmed. The memory device subsequently routes the data to the redundant memory cells instead of the defective memory cells. A system including a programming machine and the programmable non-volatile memory device, and methods for programming such memory devices, are also disclosed.

摘要翻译： 可编程非易失性存储器件包括可寻址存储器单元的存储器阵列和用于替换存储器阵列中的有缺陷的存储器单元的多个冗余存储器单元。 为了对存储器件进行编程，将数据写入存储器阵列中的一个或多个可寻址存储单元。 在数据未被有效地写入地址存储单元的情况下，重复尝试对相同的存储单元进行编程。 存储器件包括用于计数用于编程目的的相同存储器单元被访问次数的计数器。 当达到预定数量的这种编程周期时，确定地址存储单元是有缺陷的。 此时，冗余地址匹配电路被使能以用有效编程的冗余存储器单元替换有缺陷的存储单元。 存储器件随后将数据路由到冗余存储器单元而不是有缺陷的存储器单元。 还公开了一种包括编程机器和可编程非易失性存储器件的系统以及用于编程这种存储器件的方法。

公开(公告)号：US5751647A

公开(公告)日：1998-05-12

申请号：US802376

申请日：1997-02-19

申请人： James E. O'Toole

发明人： James E. O'Toole

IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C29/44 ,  G11C29/52 ,  G11C7/00

CPC分类号： G11C29/765 ,  G11C29/04 ,  G11C29/44 ,  G11C29/52 ,  G11C29/82

摘要： A programmable non-volatile memory device includes a memory array of addressable memory cells and multiple redundant memory cells for replacing defective memory cells in the memory array. To program the memory device, data is written to one or more of the addressable memory cells in the memory array. In the event that the data is not validly written into the address memory cells, repeated attempts are made to program the same memory cells. The memory device includes a counter for counting the number of times the same memory cells are accessed for programming purposes. When a predetermined number of such programming cycles is achieved, the address memory cells are determined to be defective. A redundancy address matching circuit is enabled at this point to replace the defective memory cells with redundant memory cells that can be validly programmed. The memory device subsequently routes the data to the redundant memory cells instead of the defective memory cells. A system including a programming machine and the programmable non-volatile memory device, and methods for programming such memory devices, are also disclosed.

公开(公告)号：US5355028A

公开(公告)日：1994-10-11

申请号：US965801

申请日：1992-10-23

申请人： James E. O'Toole

发明人： James E. O'Toole

IPC分类号： G05F3/24 ,  G11C5/14 ,  H03K19/00 ,  H03K19/0948 ,  H03K17/16

CPC分类号： G11C5/146 ,  G05F3/24 ,  H03K19/0013 ,  H03K19/0948

摘要： A complementary MOS buffer and amplifier stage is described herein and is useful for operation in a pump circuit of the type where an integrated circuit substrate is driven above Vcc or below ground potential. This operation serves to minimize parasitic capacitance loading and stabilize MOS device thresholds and consumes very little power. The CMOS buffer and amplifier stage includes first and second complementary input transistors cascaded to drive, respectively, first and second complementary output transistors, and lumped resistance means are connected in series between the first and second complementary input transistors and between the gate electrodes of the first and second complementary output transistors. The resistance means are operative in combination with the capacitance generated at the gate electrodes of the first and second output transistors to generate a circuit time constant that turns one of the first and second complementary output transistors completely off before the other complementary output transistor turns on. This operation completely eliminates crossover currents in the output of the buffer and amplifier stage which would otherwise represent undesirable power losses in the circuit. Advantageously, the resistance means, R, is provided in a preferred embodiment of the invention using one or more long channel MOS transistors connected between the gate electrodes of the first and second complementary output transistors and these devices operate in such a manner as to minimize parasitic capacitance introduced across the resistance means when the buffer and amplifier stage is switched from one to the other of its two conductive states.

摘要翻译： 这里描述了互补MOS缓冲器和放大器级，并且对于在集成电路衬底被驱动到高于Vcc或低于地电位的类型的泵电路中的操作是有用的。 该操作用于最小化寄生电容负载并稳定MOS器件阈值并消耗很少的功率。 CMOS缓冲器和放大器级包括级联以驱动第一和第二互补输出晶体管的第一和第二互补输入晶体管，并且集总电阻装置串联连接在第一和第二互补输入晶体管之间以及第一和第二互补输入晶体管的栅电极之间 和第二互补输出晶体管。 电阻装置与在第一和第二输出晶体管的栅电极处产生的电容相结合地产生电路时间常数，使得第一和第二互补输出晶体管之一在另一互补输出晶体管导通之前完全关闭。 该操作完全消除了缓冲器和放大器级的输出中的交叉电流，否则这将导致电路中的不期望的功率损耗。 有利地，电阻装置R在本发明的优选实施例中使用连接在第一和第二互补输出晶体管的栅电极之间的一个或多个长沟道MOS晶体管提供，并且这些器件以使寄生 当缓冲器和放大器级从其两个导通状态中的一个切换到另一个时，跨过电阻装置引入的电容。

公开(公告)号：US4586170A

公开(公告)日：1986-04-29

申请号：US600208

申请日：1984-04-16

申请人： James E. O'Toole ,  Robert J. Proebsting

发明人： James E. O'Toole ,  Robert J. Proebsting

IPC分类号： G11C29/00 ,  G11C29/44 ,  G11C13/00

CPC分类号： G11C29/835 ,  G11C29/44

摘要： A test circuit (10) for a semiconductor memory is provided. The semiconductor memory includes a redundant decoder (70) for receiving memory address signals (66, 68) which is connected to a redundant circuit element via a signal line (72). The redundant decoder (70) can be programmed in accordance with the address of a defective circuit element, such that when the decoder (70) is addressed by the memory address signals (66, 68) the decoder (70) selects a predetermined redundant circuit element. The test circuit (10) generates an output signal (14) indicating that the circuit element selected by the decoder (70) is a redundant circuit element. The output signal (14) is applied to an indicator circuit (16) which is enabled in a test mode by an abnormal condition detector (26). The output (18) of indicator circuit (16) is applied to an external pin (20).

摘要翻译： 提供了一种用于半导体存储器的测试电路（10）。 半导体存储器包括用于经由信号线（72）连接到冗余电路元件的存储器地址信号（66,68）的冗余解码器（70）。 可以根据缺陷电路元件的地址对冗余解码器（70）进行编程，使得当解码器（70）由存储器地址信号（66,68）寻址时，解码器（70）选择预定的冗余电路 元件。 测试电路（10）产生指示由解码器（70）选择的电路元件是冗余电路元件的输出信号（14）。 输出信号（14）被施加到由异常状况检测器（26）在测试模式中使能的指示器电路（16）。 指示电路（16）的输出（18）被施加到外部引脚（20）。