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公开(公告)号：US06552396B1
公开(公告)日：2003-04-22
申请号：US09524295
申请日：2000-03-14
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L21/84
摘要： An SOI multiple FET structure is provided that comprises a substrate having a substrate layer on an insulator layer. The SOI multiple FET structure includes distal diffusion regions in the substrate layer and a central diffusion region in the substrate layer. The central diffusion region has a width and extends from a surface of the substrate layer downward into contact with the insulator layer along a portion of the width and extends only partially into the substrate layer along another portion of the width. The SOI multiple FET structure also includes a pair of gates on the surface of the substrate layer each overlapping one of the distal diffusion regions and the central diffusion region; and a pair of body regions in the substrate layer each under one of the gates for forming a channel between the one of the distal diffusion regions and the central diffusion region. The body regions are in electrical communication under the another portion of the width of the central diffusion region. Methods for forming the SOI multiple FET structure are also provided.
摘要翻译： 提供了SOI多FET结构，其包括在绝缘体层上具有衬底层的衬底。 SOI多FET结构包括衬底层中的远端扩散区域和衬底层中的中心扩散区域。 中心扩散区具有宽度并且从衬底层的表面向下延伸，沿着宽度的一部分与绝缘体层接触，并且沿宽度的另一部分仅部分地延伸到衬底层中。 SOI多FET结构还包括在衬底层的表面上的一对栅极，每个栅极重叠远端扩散区域和中心扩散区域之一; 以及在所述基板层中的一个所述栅极之间的一对体区，用于在所述远侧扩散区域和所述中央扩散区域中的一个之间形成沟道。 身体区域在中央扩散区域的宽度的另一部分下电连通。 还提供了形成SOI多FET结构的方法。
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公开(公告)号：US06333230B1
公开(公告)日：2001-12-25
申请号：US09571055
申请日：2000-05-15
IPC分类号： H01L21336
CPC分类号： H01L29/66621 , H01L21/2251 , H01L29/7834
摘要： A method of fabricating a semiconductor device comprising: forming a trench on the face of a silicon substrate of a first conductivity type; depositing a conformal silicon layer of a second conductivity type into the trench; etching away the silicon layer of a second conductivity type selectively to leave portions of the silicon layer in the trench; annealing to drive dopant from the portions of the silicon layer through the walls of the trench into adjacent areas of the silicon substrate; and forming a gate structure in the trench, and source and drain diffusion regions in said silicon substrate on opposing sides of said gate structure.
摘要翻译： 一种制造半导体器件的方法，包括：在第一导电类型的硅衬底的表面上形成沟槽; 将第二导电类型的共形硅层沉积到沟槽中; 蚀刻掉第二导电类型的硅层以选择性地留下沟槽中的硅层的部分; 退火以将掺杂剂从硅层的部分通过沟槽的壁驱动到硅衬底的相邻区域中; 以及在所述沟槽中形成栅极结构，以及在所述硅衬底中在所述栅极结构的相对侧上的源极和漏极扩散区域。
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公开(公告)号：US07102166B1
公开(公告)日：2006-09-05
申请号：US10907942
申请日：2005-04-21
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L27/0922 , H01L27/1203 , H01L27/1207 , H01L29/045
摘要： A hybrid orientation semiconductor structure and method of forming the same. The structure includes (a) a semiconductor substrate comprising a first semiconductor material having a first lattice orientation; (b) a back gate region on the semiconductor substrate; (c) a back gate dielectric layer on the back gate region; (d) a semiconductor region on the back gate dielectric layer, wherein the semiconductor region is electrically insulated from the back gate region by the back gate dielectric layer, and wherein the semiconductor region comprises a second semiconductor material having a second lattice orientation different from the first lattice orientation; and (e) a field effect transistor (FET) formed on the semiconductor region, wherein changing a voltage potential applied to the back gate region causes a change in a threshold voltage of the FET.
摘要翻译： 一种混合取向半导体结构及其形成方法。 该结构包括（a）包括具有第一晶格取向的第一半导体材料的半导体衬底; （b）半导体衬底上的背栅区; （c）背栅极区上的背栅介质层; （d）背栅电介质层上的半导体区域，其中半导体区域通过背栅介质层与背栅区电绝缘，并且其中半导体区域包括具有不同于第二晶格取向的第二晶格取向的第二半导体材料 第一格方位; 和（e）形成在半导体区域上的场效应晶体管（FET），其中改变施加到背栅区的电压电位导致FET的阈值电压的变化。
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公开(公告)号：US06475838B1
公开(公告)日：2002-11-05
申请号：US09525103
申请日：2000-03-14
IPC分类号： H01L2162
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/0629 , H01L27/0805 , H01L27/1203 , H01L29/66772 , H01L29/78612 , H01L29/94
摘要： A decoupling capacitor and methods for forming the same are provided. In a first aspect, the decoupling capacitor is formed during a process for forming first and second type FETs on a common substrate that comprises a plurality of implant steps for doping channels and diffusions of the first and second type FETs. In a second aspect, a method is provided for forming the novel decoupling capacitor that includes the steps of forming a mandrel layer on a substrate, including forming openings in the mandrel layer and disposing a first type dopant into the substrate through the openings. Thereafter, an epitaxial layer is formed in the openings on the substrate, an insulator layer is formed in the openings on the epitaxial layer and a gate is formed in the openings on the insulator layer. The mandrel layer is removed and the first type dopant is disposed into the substrate abutting the first type dopant in the substrate that was disposed through the openings. During this step the first type dopant is disposed into the gate. The substrate having the first type dopant comprises one terminal of the capacitor and the gate comprises another terminal of the capacitor.
摘要翻译： 提供去耦电容器及其形成方法。 在第一方面，去耦电容器在用于在公共衬底上形成第一和第二类型FET的工艺中形成，该公共衬底包括用于掺杂第一和第二类型FET的沟道和扩散的多个注入步骤。 在第二方面，提供了一种用于形成新型去耦电容器的方法，该方法包括以下步骤：在基底上形成心轴层，包括在心轴层中形成开口，并通过开口将第一类型掺杂剂设置到基底中。 此后，在衬底上的开口中形成外延层，在外延层的开口中形成绝缘体层，并在绝缘体层的开口中形成栅极。 去除心轴层，并且将第一类型掺杂剂设置在与通过开口设置的衬底中邻接第一类型掺杂剂的衬底中。 在该步骤期间，将第一类型的掺杂剂设置在栅极中。 具有第一类型掺杂物的衬底包括电容器的一个端子，并且栅极包括电容器的另一个端子。
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45.发明授权Method of fabricating high voltage fully depleted SOI transistor and structure thereof 失效制造高电压全耗尽SOI晶体管的方法及其结构公开(公告)号：US07745879B2
公开(公告)日：2010-06-29
申请号：US11872953
申请日：2007-10-16
IPC分类号： H01L29/43 , H01L29/786
CPC分类号： H01L29/78624 , H01L29/66772 , H01L29/78612
摘要： A method of fabricating a high voltage fully depleted silicon-on-insulator (FD SOI) transistor, the FD SOI transistor having a structure including a region within a body on which a gate structure is disposed. The region includes a channel separating the source region and the drain region. Above the source region is disposed a carrier recombination element, which abuts the gate structure and is electrically connected to the region via the channel. The drain region is lightly doped and ballasted to increase breakdown voltage. The FD SOI may be fabricated by forming a body with a thin silicon layer disposed on a buried oxide (BOX). Alternatively, the body may be formed using a partially depleted (PD) SOI where the region formed therein has a reduced thickness in comparison to the overall thickness of the PD SOI.
摘要翻译： 一种制造高电压完全耗尽的绝缘体上硅（FD SOI）晶体管的方法，所述FD SOI晶体管具有包括在其中设置栅极结构的主体内的区域的结构。 该区域包括分离源极区域和漏极区域的沟道。 在源极区上方设置有载流子复合元件，该载流子复合元件邻接栅极结构，并且经由沟道电连接到该区域。 漏极区域被轻掺杂并镇流以增加击穿电压。 可以通过形成具有设置在掩埋氧化物（BOX）上的薄硅层的主体来制造FD SOI。 或者，可以使用部分耗尽（PD）SOI形成主体，其中形成在其中的区域与PD SOI的总厚度相比具有减小的厚度。
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公开(公告)号：US06943405B2
公开(公告)日：2005-09-13
申请号：US10604206
申请日：2003-07-01
申请人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
发明人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
IPC分类号： H01L21/308 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/00 , H01L29/76
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译： 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。
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47.发明授权Semiconductor devices having tensile and/or compressive stress and methods of manufacturing 有权具有拉伸和/或压缩应力的半导体器件和制造方法公开(公告)号：US09368410B2
公开(公告)日：2016-06-14
申请号：US12033280
申请日：2008-02-19
IPC分类号： H01L29/78 , H01L21/762 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76205 , H01L21/823878 , H01L29/7846
摘要： A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.
摘要翻译： 公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。 该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。 该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。 第一氧化沟槽在通道中产生应变分量以增加器件性能。
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公开(公告)号：US08617412B2
公开(公告)日：2013-12-31
申请号：US12966370
申请日：2010-12-13
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译： 本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。 纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。 纳米线结构可以包括多个垂直堆叠的水平纳米线。
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公开(公告)号：US20120168873A1
公开(公告)日：2012-07-05
申请号：US12984773
申请日：2011-01-05
IPC分类号： H01L21/70 , G06F17/50 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/26586 , H01L21/823807 , H01L29/66659
摘要： Transmission gates, methods of fabricating transmission gates, and design structures for a transmission gate. The transmission gate includes an n-channel field effect transistor characterized by terminals that are asymmetrically doped and a p-channel field effect transistor characterized by terminals that are asymmetrically doped.
摘要翻译： 传输门，制造传输门的方法和传输门的设计结构。 传输门包括n沟道场效应晶体管，其特征在于不对称掺杂的端子和由不对称掺杂的端子表征的p沟道场效应晶体管。
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公开(公告)号：US20110193163A1
公开(公告)日：2011-08-11
申请号：US12702684
申请日：2010-02-09
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： A field effect device includes a channel region disposed on a silicon on insulator (SOI) layer, a gate portion disposed on the channel region, a source region disposed on the SOI layer and connected to the channel region having a horizontal surface and a vertical surface, the vertical surface arranged perpendicular to a linear axis of the device, a silicide portion that includes the horizontal surface and vertical surface of the source region, a contact including a metallic material in contact with the horizontal surface and vertical surface of the source region, and a drain region connected to the channel region disposed on the SOI layer.
摘要翻译： 场效应器件包括设置在绝缘体上硅（SOI）层上的沟道区域，设置在沟道区上的栅极部分，设置在SOI层上的源极区域，并连接到具有水平表面和垂直表面的沟道区域 垂直于装置的线性轴排列的垂直表面，包括源区域的水平表面和垂直表面的硅化物部分，包括与源区域的水平表面和垂直表面接触的金属材料的触点， 以及连接到设置在SOI层上的沟道区的漏极区。
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