公开(公告)号：US08122273B2

公开(公告)日：2012-02-21

申请号：US11870575

申请日：2007-10-11

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith Williams ,  Charles S. Woodruff

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/26

摘要： A method and structure to optimize computational efficiency in a low-power environment. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a component to determine an optimal point for maximizing computational efficiency in a low-power environment, and a component to selectively control operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The design structure further includes at least one of a component for controlling a frequency of a clock signal transmitted to the at least one processing unit in accordance with the determined optimal point, and a component for determining a present power available.

摘要翻译： 一种在低功耗环境下优化计算效率的方法和结构。 设计结构体现在在设计过程中使用的机器可读介质中。 该设计结构包括确定用于在低功率环境中最大化计算效率的最佳点的组件，以及根据所确定的最佳点选择性地控制多个处理单元的至少一个处理单元的操作的组件。 该设计结构还包括用于根据确定的最佳点来控制发送到至少一个处理单元的时钟信号的频率的组件和用于确定当前可用功率的组件中的至少一个。

公开(公告)号：US07903493B2

公开(公告)日：2011-03-08

申请号：US12109379

申请日：2008-04-25

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Nitin Sharma ,  Sebastian T. Ventrone ,  Charles S. Woodruff

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Nitin Sharma ,  Sebastian T. Ventrone ,  Charles S. Woodruff

IPC分类号： G11C5/14

CPC分类号： G11C5/143

摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a threshold register having a counter, a count register, and a non-volatile storage for storing a state when a value of the count register equals or exceeds a value of the threshold register. Also provided is a method of predicting and/or estimating a power cycle duration in order to save a state in non-volatile memory and a circuit. The method includes setting a threshold value; determining that the threshold value has been equaled or exceeded; and saving the state in the non-volatile memory at a first checkpoint based on the threshold value being equaled or exceeded.

摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括具有计数器，计数寄存器和非易失性存储器的阈值寄存器，用于当计数寄存器的值等于或超过阈值寄存器的值时存储状态。 还提供了一种预测和/或估计功率周期持续时间以便将状态保存在非易失性存储器和电路中的方法。 该方法包括设置阈值; 确定阈值已经相等或超过; 并且基于所述阈值相等或超过，在第一检查点处将所述状态保存在所述非易失性存储器中。

公开(公告)号：US07898286B2

公开(公告)日：2011-03-01

申请号：US12369066

申请日：2009-02-11

申请人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

发明人： Igor Arsovski ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

IPC分类号： H03K19/00

CPC分类号： G01R31/31725

摘要： Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.

摘要翻译： 用于管芯或芯片的跨管芯连接结构和方法包括具有缓冲器驱动器和旁路的缓冲器元件以及耦合到缓冲器元件的控制线，以便为每个相应的缓冲元件选择缓冲器驱动器和旁路中的一个。 逻辑网络被布置成具有缓冲元件以形成功能路径，测试单元被构造和布置以测试功能路径并耦合到控制线，以及配置存储寄存器，用于设置所选缓冲器驱动器和 绕过每个通过的功能路径。

公开(公告)号：US07872692B2

公开(公告)日：2011-01-18

申请号：US12056795

申请日：2008-03-27

申请人： Ahmed Y. Ginawi ,  Casey J. Grant ,  Christopher Ro ,  Sebastian T. Ventrone

发明人： Ahmed Y. Ginawi ,  Casey J. Grant ,  Christopher Ro ,  Sebastian T. Ventrone

IPC分类号： H04N5/50 ,  H04N5/44

CPC分类号： H04N7/163 ,  H04N21/4383 ,  H04N21/4394 ,  H04N21/44008 ,  H04N21/472 ,  H04N21/812

摘要： A design structure for systems for switching a displayed signal for a display between a plurality of signals are disclosed. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes: a system for switching a displayed signal for a display between a plurality of signals, the system including: a microcontroller; a chooser for setting a primary signal from a plurality of program-variable signals; a monitor tuner coupled to the microcontroller for tuning the primary signal during switching of the displayed signal from the primary signal to a secondary signal; a detector coupled to the monitor tuner and the microcontroller for detecting a predetermined condition in the primary signal; and a selector coupled to the microcontroller for switching the displayed signal from the secondary signal to the primary signal upon occurrence of the predetermined condition.

摘要翻译： 公开了用于在多个信号之间切换用于显示的显示信号的系统的设计结构。 在一个实施例中，设计结构体现在用于设计，制造或测试集成电路的机器可读介质中，并且包括：用于在多个信号之间切换用于显示的显示信号的系统，所述系统包括：微控制器 ; 用于从多个可编程信号设置主信号的选择器; 耦合到微控制器的监视器调谐器，用于在将所显示的信号从主信号切换到辅助信号期间调谐主信号; 耦合到所述监视器调谐器和所述微控制器的检测器，用于检测所述主信号中的预定条件; 以及耦合到微控制器的选择器，用于在发生预定条件时将显示的信号从次级信号切换到主信号。

公开(公告)号：US20100333058A1

公开(公告)日：2010-12-30

申请号：US12875517

申请日：2010-09-03

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

IPC分类号： G06F17/50

CPC分类号： G01R31/31718 ,  G11C17/14 ,  G11C29/88 ,  H03K19/17764 ,  H03K19/17796

摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAs) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.

摘要翻译： 一种提高现场可编程门阵列（FPGA）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。 测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。 为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。 用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。 结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

公开(公告)号：US20100269166A1

公开(公告)日：2010-10-21

申请号：US12621570

申请日：2009-11-19

申请人： Mariette Awad ,  Deanna C. Lim ,  Pascal A. Nsame ,  Dancyand J. Singley ,  Sebastian T. Ventrone

发明人： Mariette Awad ,  Deanna C. Lim ,  Pascal A. Nsame ,  Dancyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F21/20

CPC分类号： G06F21/55 ,  G06F21/31

摘要： In one embodiment, the invention is a method and apparatus for secure and reliable computing. One embodiment of an end-to-end security system for protecting a computing system includes a processor interface coupled to at least one of an application processor and an accelerator of the computing system, for receiving requests from the at least one of the application processor and the accelerator, a security processor integrating at least one embedded storage unit and connected to the processor interface with a tightly coupled memory unit for performing at least one of: authenticating, managing, monitoring, and processing the requests, and a data interface for communicating with a display, a network, and at least one embedded storage unit for securely holding at least one of data and programs used by the at least one of the application processor and the accelerator.

摘要翻译： 在一个实施例中，本发明是用于安全和可靠计算的方法和装置。 用于保护计算系统的端到端安全系统的一个实施例包括耦合到计算系统的应用处理器和加速器中的至少一个的处理器接口，用于接收来自应用处理器的至少一个和 加速器，集成至少一个嵌入式存储单元并且与处理器接口连接的紧密耦合的存储器单元的安全处理器，用于执行以下至少一个：认证，管理，监视和处理请求，以及数据接口，用于与 显示器，网络和至少一个嵌入式存储单元，用于安全地保持应用处理器和加速器中的至少一个使用的数据和程序中的至少一个。

公开(公告)号：US07793251B2

公开(公告)日：2010-09-07

申请号：US11275536

申请日：2006-01-12

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

IPC分类号： G06F17/50

CPC分类号： G01R31/31718 ,  G11C17/14 ,  G11C29/88 ,  H03K19/17764 ,  H03K19/17796

摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.

摘要翻译： 一种提高现场可编程门阵列（FPGAS）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。 测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。 为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。 用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。 结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

公开(公告)号：US07765351B2

公开(公告)日：2010-07-27

申请号：US11684687

申请日：2007-03-12

申请人： Pascal A. Nsame ,  Anthony D. Polson ,  Nancy H. Pratt ,  Sebastian T. Ventrone

发明人： Pascal A. Nsame ,  Anthony D. Polson ,  Nancy H. Pratt ,  Sebastian T. Ventrone

IPC分类号： G06F12/00

CPC分类号： G06F9/526 ,  G06F9/544 ,  G06F15/167

摘要： A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.

摘要翻译： 用于动态管理系统内信号量数据移动的系统和方法。 该系统包括但不限于通过网络通信的多个功能单元，与网络上的多个功能单元的存储设备通信，以及与多个功能单元通信的至少一个信号量存储单元，以及 存储设备通过网络。 多个功能单元包括多个功能单元存储单元。 存储器件包括多个存储器件存储器位置。 所述至少一个信号量存储单元包括多个信号量存储单元存储单元。 所述至少一个信号量存储单元控制所述多个功能单元存储器位置，所述多个存储器设备存储器位置，所述多个信号量存储单元存储器位置中的所述信号量数据的动态移动以及所述多个功能单元存储单元的任何组合。

公开(公告)号：US20090307637A1

公开(公告)日：2009-12-10

申请号：US12135250

申请日：2008-06-09

申请人： Susan K. Lichtensteiger ,  Michael R. Ouellette ,  Raymond W. M. Schuppe ,  Sebastian T. Ventrone

发明人： Susan K. Lichtensteiger ,  Michael R. Ouellette ,  Raymond W. M. Schuppe ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/72

摘要： Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.

摘要翻译： 设计和测试还原逻辑的方法，用于将功能管理逻辑电路的存储元件恢复为值。 在一个实施方式中，所公开的设计方法包括提供逻辑电路的设计，当被实例化时，逻辑电路将具有多个状态，可以在重新启动逻辑电路时将其返回。 由存储元件保存的值被确定并用于将存储元件分类成允许开发还原逻辑的类别，恢复逻辑将恢复适合于特定供电的功率管理逻辑电路的状态。 恢复逻辑设计通过对硬件描述语言进行建模和功耗管理的逻辑电路进行测试，并通过多个测试用例模拟状态数量。 如果设计和测试成功，则可以将恢复逻辑优化为实例化为实际的集成电路。

公开(公告)号：US20090239313A1

公开(公告)日：2009-09-24

申请号：US12343686

申请日：2008-12-24

申请人： Theodoros Anemikos ,  Ezra D.B. Hall ,  Sebastian T. Ventrone

发明人： Theodoros Anemikos ,  Ezra D.B. Hall ,  Sebastian T. Ventrone

IPC分类号： G06F17/50 ,  H01L21/66

CPC分类号： G06F17/5045 ,  G01R31/2884 ,  G01R31/3025 ,  G06F2217/12 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s).

摘要翻译： 公开了设计和制造系统以及相关方法的实施例，其允许在晶片制造期间进行设计分析和插入过程内监控电路。 这些实施例使用预定义的内部过程监视电路库和将不同监控电路与不同IC芯片组件链接的互相关表。 具体地，这些实施例分析集成电路芯片设计数据以识别设计到芯片中的部件。 然后，从库中选择一个或多个进程内监控电路，并且修改设计数据以包括所选择的监视电路。