公开(公告)号：US07558122B2

公开(公告)日：2009-07-07

申请号：US11938922

申请日：2007-11-13

申请人： Dae-Han Kim ,  Jung-Woo Lee

发明人： Dae-Han Kim ,  Jung-Woo Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： A flash memory device and a method of erasing memory cells in a flash memory device are provided. A first post program operation is performed on erased memory cells having a threshold voltage lower than a first program verify voltage. A second post program operation is performed on erased memory cells having a threshold voltage lower than a second program verify voltage. The second program verify voltage is lower than the first program verify voltage.

摘要翻译： 提供闪速存储器件和擦除闪速存储器件中的存储器单元的方法。 对具有低于第一编程验证电压的阈值电压的擦除存储单元执行第一后编程操作。 在具有低于第二编程验证电压的阈值电压的擦除存储器单元上执行第二后编程操作。 第二个程序验证电压低于第一个程序验证电压。

公开(公告)号：US07534720B2

公开(公告)日：2009-05-19

申请号：US11608500

申请日：2006-12-08

申请人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

发明人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835

摘要： Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.

摘要翻译： 制造在互连孔的下侧具有斜面的半导体器件的方法包括依次形成在具有下导电层的半导体衬底上的蚀刻停止层和层间电介质层。 蚀刻停止层的一部分通过选择性蚀刻层间电介质层而被曝光。 通过去除暴露的蚀刻停止层的部分，在蚀刻停止层中形成台阶。 并且，该步骤形成在暴露的蚀刻停止层的凹陷部分和被层间介电层覆盖的蚀刻停止层的凸起部分之间的边界处。 去除层间绝缘层的一部分以暴露蚀刻停止层的凸起部分的部分。 并且，各向异性蚀刻暴露的凹部和凸起部分以暴露下导电层并形成具有斜面的互连孔，其中斜面由互连孔的下侧的残留蚀刻停止层制成。

公开(公告)号：US20090085193A1

公开(公告)日：2009-04-02

申请号：US12010643

申请日：2008-01-28

申请人： Seung-Hyun Cho ,  Seung-Chul Kim ,  Sang-Soo Lee ,  Jung-Woo Lee

发明人： Seung-Hyun Cho ,  Seung-Chul Kim ,  Sang-Soo Lee ,  Jung-Woo Lee

IPC分类号： H01L23/373 ,  H05K1/11

CPC分类号： H05K3/285 ,  B82Y10/00 ,  H01L23/373 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/15311 ,  H05K1/0209 ,  H05K3/3452 ,  H05K2201/026 ,  Y10S977/742

摘要： A heat-releasing printed circuit board and semiconductor chip package are disclosed. The heat-releasing printed circuit board includes an insulation layer, on a surface of which a circuit pattern is formed, and a solder resist, which is stacked on the insulation layer, where the solder resist contains carbon nanotubes. The heat-releasing printed circuit board allows the heat generated in a semiconductor chip to be dispersed in several directions of the board or package, to improve heat-releasing property.

摘要翻译： 公开了一种散热印刷电路板和半导体芯片封装。 散热印刷电路板包括在其表面上形成电路图案的绝缘层和层叠在绝缘层上的阻焊剂，其中阻焊剂包含碳纳米管。 散热印刷电路板允许在半导体芯片中产生的热分散在板或封装的多个方向上，以提高散热性能。

公开(公告)号：US20080102015A1

公开(公告)日：2008-05-01

申请号：US11878155

申请日：2007-07-20

申请人： Jeung-Ku Kang ,  Seong-Ho Yang ,  Hyun-Seok Kim ,  Kyu-Sung Han ,  Se-Yun Kim ,  Jung-Woo Lee ,  Weon-Ho Shin ,  Jun-Hyeon Bae

发明人： Jeung-Ku Kang ,  Seong-Ho Yang ,  Hyun-Seok Kim ,  Kyu-Sung Han ,  Se-Yun Kim ,  Jung-Woo Lee ,  Weon-Ho Shin ,  Jun-Hyeon Bae

IPC分类号： C01B21/00

CPC分类号： B82Y40/00 ,  B01J21/185 ,  B01J23/75 ,  B01J23/755 ,  B01J37/0203 ,  B01J37/16 ,  B82Y30/00 ,  C01B3/0021 ,  C01B32/162 ,  H01J1/304 ,  H01J9/025 ,  H01J2201/30449 ,  H01J2201/30469 ,  Y02E60/325

摘要： The present invention relates to a method for manufacturing a transition metal-carbon nanotube hybrid material using nitrogen as a medium. The present invention is characterized in that nitrogen-added carbon nanotube is grown in the presence of metal catalyst particles by reacting an hydrocarbon gas with a nitrogen gas by a chemical vapor deposition (CVD) and a transition metal-carbon nanotube hybrid material where a transition metal is uniformly attached to the entire carbon nanotube structure in which nitrogen with a great chemical reactivity is added as heterogeneous elements is chemically manufactured. Therefore, the present invention does not use an acid treatment required to attach transition-metal atoms to the carbon-nanotube, a surface treating process using a surfactant and the like and an inhibitor for preventing the coagulation of the transition metal so that a simplification of the process is obtained and the method is an environment-friendly method. The transition metal-carbon nanotube hybrid material manufactured by the above can be applied variously as a hydrogen storage material, a catalyst material, an electric field emission device and an electrode material.

摘要翻译： 本发明涉及使用氮作为介质制造过渡金属 - 碳纳米管混合材料的方法。 本发明的特征在于，通过化学气相沉积（CVD）和过渡金属 - 碳纳米管混合材料使碳氢化合物气体与氮气反应，在金属催化剂颗粒的存在下生长氮添加碳纳米管，其中过渡 金属均匀地附着在整个碳纳米管结构上，其中加入具有大的化学反应性的氮作为异质元素是化学制造的。 因此，本发明不使用将过渡金属原子附着在碳纳米管上所需的酸处理，使用表面活性剂等的表面处理方法和防止过渡金属凝结的抑制剂， 获得该过程，并且该方法是环境友好的方法。 由上述制造的过渡金属 - 碳纳米管混合材料可以用作储氢材料，催化剂材料，电场发射装置和电极材料。

公开(公告)号：US20070082484A1

公开(公告)日：2007-04-12

申请号：US11608500

申请日：2006-12-08

申请人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

发明人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835

摘要： Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.

摘要翻译： 制造在互连孔的下侧具有斜面的半导体器件的方法包括依次形成在具有下导电层的半导体衬底上的蚀刻停止层和层间电介质层。 蚀刻停止层的一部分通过选择性蚀刻层间电介质层而被曝光。 通过去除暴露的蚀刻停止层的部分，在蚀刻停止层中形成台阶。 并且，该步骤形成在暴露的蚀刻停止层的凹陷部分和被层间介电层覆盖的蚀刻停止层的凸起部分之间的边界处。 去除层间绝缘层的一部分以暴露蚀刻停止层的凸起部分的部分。 并且，各向异性蚀刻暴露的凹部和凸起部分以暴露下导电层并形成具有斜面的互连孔，其中斜面由互连孔的下侧的残留蚀刻停止层制成。

公开(公告)号：US20050088141A1

公开(公告)日：2005-04-28

申请号：US10959011

申请日：2004-10-05

申请人： Kyung-Sang Lee ,  Jung-Woo Lee ,  Moon-Young Chai

发明人： Kyung-Sang Lee ,  Jung-Woo Lee ,  Moon-Young Chai

IPC分类号： A45F5/00 ,  A45F5/02 ,  H01M2/10 ,  H01M10/42 ,  H01M10/46 ,  H02J7/00 ,  H02J7/02

CPC分类号： H02J7/0044 ,  A45F5/00 ,  A45F5/02 ,  A45F5/021 ,  A45F2005/006 ,  A45F2005/025 ,  A45F2200/0516 ,  H01M2/1022 ,  H01M10/46 ,  H02J5/00 ,  H02J7/0013 ,  H02J7/0052 ,  H02J7/02

摘要： Disclosed herein is a portable charger for a mobile phone. The portable charger includes a front housing, a rear housing, a belt clip, a fastening unit, a pair of clamps, a release button, an interface connector, a secondary battery and a charge control unit. The portable charger is easy to carry, can easily charge the battery of the mobile phone with direct current power charged in a secondary battery, and can simultaneously charge the secondary battery and the battery of the mobile phone using a travel adaptor.

摘要翻译： 本文公开了一种用于移动电话的便携式充电器。 便携式充电器包括前壳体，后壳体，皮带夹，紧固单元，一对夹具，释放按钮，接口连接器，二次电池和充电控制单元。 便携式充电器易于携带，可以用二次电池中的直流电源容易地对手机的电池充电，并且可以使用旅行适配器同时为二次电池和手机的电池充电。

公开(公告)号：US20050054192A1

公开(公告)日：2005-03-10

申请号：US10910922

申请日：2004-08-04

申请人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

发明人： Ki-Ho Kang ,  Hyeok-Sang Oh ,  Jung-Woo Lee ,  Dae-Keun Park

IPC分类号： H01L21/28 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835

摘要： Methods of manufacturing semiconductor devices having slopes at lower sides of an interconnection hole include an etch-stop layer and an interlayer dielectric layer sequentially formed on a semiconductor substrate having the lower conductive layer. Portions of the etch-stop layer are exposed by selectively etching the interlayer dielectric layer. A step is formed in the etch-stop layer by removing portions of the exposed etch-stop layer. And, the step is formed at a boundary between a recessed portion of the exposed etch-stop layer and a raised portion of the etch-stop layer covered with the interlayer dielectric layer. Portions of the interlayer dielectric layer are removed to expose portions of the raised portion of the etch-stop layer. And, the exposed recessed and raised portions are anisotropically etched to expose the lower conductive layer and to form the interconnection hole having the slopes, wherein the slopes are made of a residual etch-stop layer at the lower sides of the interconnection hole.

摘要翻译： 制造在互连孔的下侧具有斜面的半导体器件的方法包括依次形成在具有下导电层的半导体衬底上的蚀刻停止层和层间电介质层。 蚀刻停止层的一部分通过选择性蚀刻层间电介质层而被曝光。 通过去除暴露的蚀刻停止层的部分，在蚀刻停止层中形成台阶。 并且，该步骤形成在暴露的蚀刻停止层的凹陷部分和被层间介电层覆盖的蚀刻停止层的凸起部分之间的边界处。 去除层间绝缘层的一部分以暴露蚀刻停止层的凸起部分的部分。 并且，各向异性蚀刻暴露的凹部和凸起部分以暴露下导电层并形成具有斜面的互连孔，其中斜面由互连孔的下侧的残留蚀刻停止层制成。